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[[SystemVerilog]],
==See also==
*[[e (verification language)|e]]<ref>{{Cite book |last1=Iman |first1=Sasan |title=The e Hardware Verification Language (Information Technology: Transmission, Processing & Storage) |last2=Joshi |first2=Sunita |date=May 8, 2007 |publisher=Springer |isbn=978-1402080234}}</ref>
*[[SystemC]]<ref>{{Cite web |title=systemc.org |url=https://systemc.org/ |access-date=2024-09-10 |website=systemc.org}}</ref>
*[[SystemVerilog]]<ref>{{Cite book |last=IEEE |date=February 22, 2018 |title=1800-2017 - IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language |doi=10.1109/IEEESTD.2018.8299595 |isbn=978-1-5044-4509-2 }}</ref>
*[[Property Specification Language]]<ref>{{Cite book |last=IEEE |date=2005 |title=1850-2005 –IEEE Standard for Property Specification Language (PSL) |doi=10.1109/IEEESTD.2005.97780 |isbn=0-7381-4780-X}}</ref>
*[[Python with cocotb]]<ref>{{Cite web |title=cocotb |url=https://www.cocotb.org/ |access-date=2024-09-10 |website=cocotb |language=en}}</ref>
*[[Scala with ChiselTest]]<ref>{{Cite web |title=chiseltest |url=https://index.scala-lang.org/ucb-bar/chiseltest}}</ref>
== References ==
{{reflist}}
{{DEFAULTSORT:Hardware Verification Language}}
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