Content deleted Content added
Rescuing 2 sources and tagging 1 as dead.) #IABot (v2.0.9.5 |
|||
| (3 intermediate revisions by 3 users not shown) | |||
Line 14:
The first-generation Intel APIC chip, the 82489DX, which was meant to be used with [[Intel 80486]] and early Pentium processors, is actually an external local and I/O APIC in one circuit. The Intel MP 1.4 specification refers to it as "discrete APIC" in contrast with the "integrated APIC" found in most of the Pentium processors.<ref>[http://www.intel.com/design/archives/processors/pro/docs/242016.htm Intel MultiProcessor Specification], version 1.4, page 1-4, May 1997</ref> The 82489DX had 16 interrupt lines;<ref name="Ram2001">{{cite book|author=Badri Ram|title=Adv Microprocessors Interfacing|url=https://books.google.com/books?id=eVcEWDIeTYcC&pg=PT314|year=2001|publisher=Tata McGraw-Hill Education|isbn=978-0-07-043448-6|page=314}}</ref> it also had a quirk that it could lose some ISA interrupts.<ref >{{cite web | website=freebsd.org|title=A Description of the APIC I/O Subsystem | url=http://people.freebsd.org/~fsmp/SMP/papers/apicsubsystem.txt | access-date=14 May 2023}}</ref>
In a multiprocessor 486 system, each CPU had to be paired with its own 82489DX; additionally a supplementary 82489DX had to be used as I/O APIC. The 82489DX could not emulate the 8259A (XT-PIC) so these also had to be included as physical chips for backwards compatibility.<ref>Intel MultiProcessor Specification, version 1.4, page 5-3, May 1997</ref> The 82489DX was packaged as a 132-pin [[PQFP]].<ref name="Ram2001"/> It was available for USD $26 per 1,000-unit in quantities.<ref>Intel Corporation, "New Product Focus: OEM: Interrupt Controller Optimized for Advanced Operating Systems", Microcomputer Solutions, January/February 1993, page 21</ref>
==Integrated local APICs==
Line 21:
All Intel processors starting with the P5 microarchitecture ([[P54C]]) have a built-in local APIC.<ref name="Mueller2011">{{cite book|author=Scott M. Mueller|title=Upgrading and Repairing PCs|year=2011|publisher=Que Publishing|isbn=978-0-13-268218-3|page=242|edition=20th}}</ref><ref name="timer" /> However, if the local APIC is disabled in a P5 processor, it cannot be re-enabled by software; this limitation no longer exists in the [[P6 (microarchitecture)|P6 processors]] and later ones.<ref name="timer" />
With the introduction of [[Pentium 4 HT]] and [[Pentium D]], each CPU core and each CPU thread
The [[Message Signaled Interrupts]] (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.<ref name="up">{{cite web|url=http://msdn.microsoft.com/en-us/windows/hardware/gg462964.aspx|title=Windows Hardware Dev Center|website=msdn.microsoft.com|date=June 2017 }}</ref> Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.<ref name="msi"/>
Line 28:
Another advantage of the local APIC is that it also provides a high-resolution (on the order of one [[microsecond]] or better) timer that can be used in both interval and one-off mode.<ref name="timer">Uwe Walter, Vincent Oberle [http://telematics.tm.kit.edu/publications/Files/61/walter_ibm_linux_challenge.pdf μ-second precision timer support for the Linux kernel]</ref>
The APIC timer had its initial acceptance woes. A Microsoft document from 2002 (which advocated for the adoption of [[High Precision Event Timer]] instead) criticized the LAPIC timer for having "poor resolution" and stating that "the clocks silicon is sometimes very buggy".<ref>{{Cite web |date=2002-09-20 |title=Guidelines For Providing Multimedia Timer Support |url=http://msdn.microsoft.com/en-us/library/windows/hardware/gg463347.aspx |archive-url=https://web.archive.org/web/20120728124718/http://msdn.microsoft.com/en-us/library/windows/hardware/gg463347.aspx |archive-date=2012-07-28 |url-status=
The aperiodic interrupts offered by the APIC timer are used by the [[Linux kernel]] [[tickless kernel]]
feature. This optional but default feature is new with 2.6.18. When enabled on a computer with an APIC timer, the kernel does not use the [[8253]] [[programmable interval timer]] for timekeeping.<ref>{{cite web|url=http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802|title=VMware Knowledge Base|website=kb.vmware.com|access-date=2014-02-13|archive-date=2017-02-27|archive-url=https://web.archive.org/web/20170227025032/http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802|url-status=dead}}</ref> A [[VMware]] document notes that "software does not have a reliable way to determine its frequency. Generally, the only way to determine the local APIC timer’s frequency is to measure it using the PIT or CMOS timer, which yields only an approximate result."<ref name="vmware">[http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf Timekeeping in VMware Virtual Machines (for VMware vSphere 5.0, Workstation 8.0, Fusion 4.0)] {{Webarchive|url=https://web.archive.org/web/20160626142735/http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf |date=2016-06-26 }}, page 8</ref>
==I/O APICs==
Line 56:
== Competition ==
{{further|OpenPIC and IBM MPIC}}
[[AMD]] and [[Cyrix]] once proposed a somewhat similar-in-purpose [[OpenPIC]] architecture supporting up to 32 processors;<ref>{{cite web |url=https://www.pcmag.com/encyclopedia_term/0,2542,t=OpenPIC&i=48497,00.asp |title=OpenPIC Definition from PC Magazine Encyclopedia |publisher=Pcmag.com |date=1994-12-01 |access-date=2011-11-03 }}{{Dead link|date=August 2025 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> it had at least declarative support from [[IBM]] and [[Compaq]] around 1995.<ref name="Inc.1995">{{cite journal|title=AMD, Cyrix offer up alternative SMP spec|author=Brooke Crothers|journal=[[InfoWorld]]|url=https://books.google.com/books?id=lToEAAAAMBAJ&pg=PA8|date=20 March 1995|page=8|issn=0199-6649}}</ref> No x86 motherboard was released with OpenPIC however.<ref>André D. Balsa, [http://linuxgazette.net/issue24/Article3e-7.html Note attached to "Linux Benchmarking: Part III -- Interpreting Benchmark Results"] appearing in Issue 24 of Linux Gazette, January 1998</ref> After the OpenPIC's failure in the x86 market, AMD licensed Intel's APIC for its [[AMD Athlon]] and later processors.
IBM however developed their [[OpenPIC and MPIC|MultiProcessor Interrupt Controller]] (MPIC) based on the OpenPIC register specifications.<ref>IBM [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf Multiprocessor Interrupt Controller. Data Book] {{webarchive|url=https://web.archive.org/web/20140223012746/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/%24file/mpic_db_05_16_2011.pdf |date=2014-02-23 }}</ref> MPIC was used in [[PowerPC]] based designs, including those of IBM, for instance in some [[RS/6000]] systems,<ref>Arca Systems TTAP Evaluation Facility [http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security], p. 29</ref> but also by Apple, as late as their [[Power Mac G5]]s.<ref>{{cite book|url=http://www.informit.com/articles/article.aspx?p=606582|title=Take a Look Inside the G5-Based Dual-Processor Power Mac|first=Amit|last=Singh|date=13 October 2006|via=informIT database}}</ref><ref>[https://developer.apple.com/legacy/library/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/PowerMacG5.pdf Power Mac G5 Developer Note (Legacy)], p. 26</ref>
| |||