Programmed input–output: Difference between revisions

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{{Short description|Method of CPU communication with peripheral devices}}

{{Refimprove|date=June 2013}}

'''Programmed input–output''' (also '''programmable input/output''', '''programmed input/output''', '''programmed I/O''', '''PIO''') is a method of [[data transmission]], via [[input/output]] (I/O), between a [[central processing unit]] (CPU) and a [[peripheral]] device,<ref suchname="CompArchOrg">{{cite asbook a|title=Computer [[networkArchitecture adapter]]and orOrganization |last=Hayes |first=John P. |isbn=0-07-027363-4 |date=1978 |publisher=McGraw-Hill International Book Company |pages=419}}</ref> such as a [[Parallel ATA]] storage device. Each data item transfer is initiated by an instruction in the program, involving the CPU for every transaction. In contrast, in [[direct memory access]] (DMA) operations, the CPU is uninvolved in the data transfer.

The term can refer to either [[memory-mapped I/O]] (MMIO) or port-mapped I/O (PMIO). PMIO refers to transfers using a special [[address space]] outside of normal memory, usually accessed with dedicated instructions, such as <samp>IN</samp> and <samp>OUT</samp> in [[x86]] architectures. MMIO<ref>{{cite book |last=Stallings |first=William |date=2012 |title=Computer Organization and Architecture |edition=9th |publisher=Pearson}}</ref> refers to transfers to I/O devices that are mapped into the normal address space available to the program. PMIO was very useful for early microprocessors with small address spaces, since the valuable resource was not consumed by the I/O devices.

The best known example of a PC device that uses programmed I/O is the Parallel AT Attachment (ATAPATA) interface; however, thisthe AT Attachment interface can also be operated in any of several DMA modes. Many older devices in a PC also use PIO, including legacy serial ports, legacy parallel ports when not in ECP mode, keyboard and mouse [[PS/2 port]]s, legacy Musical Instrument Digital Interface ([[MIDI]]) and [[joystick]] ports, the interval timer, and older network interfaces.

== PIO mode in the ATA interface ==

The PIO interface is grouped into different modes that correspond to different [[transfer rate]]s. The [[electrical signal]]ing among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance.

The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the DMA (and eventually [[Ultra Direct Memory Access]] ([[UDMA]]) interface was created to increase performance. The simple digital logic needed to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are unneeded as in [[embedded system]]s, or with [[field-programmable gate array]] (FPGA) chips, where PIO mode can be used with no significant performance loss.

Two additional advanced timing modes have been defined in the [[CompactFlash]] specification 2.0. Those are PIO modes 5 and 6. They are specific to CompactFlash.

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{{DEFAULTSORT:Programmed input output}}

[[Category:Input/output]]

[[Category:AT Attachment]]