Programmed input–output: Difference between revisions

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{{Short description|Method of CPU communication with peripheral devices}}

{{Refimprove|date=June 2013}}

'''Programmed input–output''' (also '''programmable input/output''', '''programmed input/output''', '''programmed I/O''', '''PIO''') is a method of [[Datadata transfer|transferringtransmission]], datavia [[input/output]] (I/O), between thea [[Centralcentral processing unit|CPU]] (CPU) and a [[peripheral]] device,<ref suchname="CompArchOrg">{{cite asbook a|title=Computer [[networkArchitecture adapter]]and orOrganization an |last=Hayes |first=John P. |isbn=0-07-027363-4 |date=1978 |publisher=McGraw-Hill International Book Company |pages=419}}</ref> such as a [[ATParallel attachment|ATA]] storage device. Each data item transfer is initiated by an instruction in the program, involving the CPU for every transaction. In contrast, in [[direct memory access]] (DMA) operations, the CPU is not involveduninvolved in the data transfer.

The term can refer to either [[Memory-mapped I/O|memory-mapped I/O]] (MMIO) or port-mapped I/O (PMIO)]]. PMIO refers to transfers using a special [[address space]] outside of normal memory, usually accessed with dedicated instructions, such as <samp>IN</samp> and <samp>OUT</samp> in [[x86]] architectures. MMIO<ref>{{cite book |last=Stallings |first=William |date=2012 |title=Computer Organization and Architecture |edition=9th |publisher=Pearson}}</ref> refers to transfers to input–output (I/O) devices that are mapped into the normal address space available to the program. PMIO was very useful for early microprocessors with small address spaces, since the valuable resource was not consumed by the I/O devices.

The best known example of a PC device that uses programmed I/O is the [[Parallel AT attachment|ATA]]Attachment (PATA) interface; however, thisthe AT Attachment interface can also be operated in any of several DMA modes. Many older devices in a PC also use PIO, including legacy serial ports, legacy parallel ports when not in ECP mode, the PS/2 keyboard and mouse ports[[PS/2 port]]s, legacy [[MIDI]] and [[joystick]] ports, the interval timer, and older network interfaces.

== PIO mode in the ATA interface ==

The PIO interface is grouped into different modes that correspond to different [[transfer rate]]s. The [[electrical signal]]ing among the different modes is similar — only the cycle time between transactions is reduced in order to achieve a higher transfer rate. All ATA devices support the slowest mode — Mode 0. By accessing the information registers (using Mode 0) on an ATA drive, the CPU is able to determine the maximum transfer rate for the device and configure the ATA controller for optimal performance.

The PIO modes require a great deal of CPU overhead to configure a data transaction and transfer the data. Because of this inefficiency, the DMA (and eventually [[UDMAUltra Direct Memory Access]] (UDMA) interface was created to increase performance. The simple digital logic requiredneeded to implement a PIO transfer still makes this transfer method useful today, especially if high transfer rates are notunneeded required likeas in [[embedded systemssystem]]s, or with [[Fieldfield-programmable gate array|FPGA]] (FPGA) chips, where PIO mode can be used withoutwith no significant performance loss.

Two additional advanced timing modes have been defined in the [[CompactFlash]] specification 2.0. Those are PIO modemodes 5 and PIO mode 6. They are specific to CompactFlash.

{| class="wikitable" style="text-align:center"

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=== PIO Mode 5 ===

A PIO Mode 5 was proposed<ref name="ATA Timing Extension For ATA-3">{{cite web |url= https://www.t10.org/ftp/t10/document.95/95-122r0.pdf |title=Proposed 22 MByte/Sec ATA Timing Extension for ATA-3 |first=Joseph |last=Chen |date=January 10, 1995 |publisher=Technical Committee T10 (X3T10) |work=T10.org |archive-url= https://web.archive.org/web/20100620052300/https://www.t10.org/ftp/t10/document.95/95-122r0.pdf |archive-date=June 1020, 2010 |url-status=live |access-date=February 19, 2020}}</ref> with operation at 22&nbsp;MB/s, but was never implemented on hard disks because CPUs of the time would have been crippled waiting for the hard disk at the proposed PIO 5 timings, and the [[Direct memory access|DMA]] standard ultimately obviated it. While no [[Hardhard disk|hard drivesdrive]] werewas ever manufactured to support this mode, some [[motherboard]] manufacturers preemptively provided [[BIOS]] support for it. PIO Mode 5 can be used with CompactFlash cards connected to IDEATA via CF-to-IDEATA adapters.

== See also ==

* [[WDMA (computer)|WDMA]] – single/multi-word DMA

* [[AT Attachment|ATA]] – ATA specification

* [[Input–outputInput/output]]

* [[Interrupt]]

* [[List of device bandwidths]]

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{{DEFAULTSORT:Programmed input output}}

[[Category:Input/output]]

[[Category:AT Attachment]]