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{{Redirect|RAM|other uses|RAM (disambiguation)}}
{{Distinguish|Random Access Memories|Random-access machine}}
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[[File:Random Access Memory HyperX.jpg|thumb|8GB [[DDR3]] RAM stick with a white [[heatsink]]]]
'''Random-access memory''' ('''RAM'''; {{IPAc-en|r|æ|m}}) is a form of [[Computer memory|electronic computer memory]] that can be read and changed in any order, typically used to store working [[Data (computing)|data]] and [[machine code]].<ref>{{cite web |title=RAM |url=https://dictionary.cambridge.org/dictionary/english/ram |website=[[Cambridge English Dictionary]] |access-date=11 July 2019}}</ref><ref>{{cite web |title=RAM |url=https://www.oxfordlearnersdictionaries.com/definition/american_english/ram_2 |website=[[Oxford Advanced Learner's Dictionary]] |access-date=11 July 2019}}</ref> A [[random
In
Non-volatile RAM has also been developed<ref>{{cite magazine|last=Gallagher|first=Sean|title=Memory that never forgets: non-volatile DIMMs hit the market|url=https://arstechnica.com/information-technology/2013/04/memory-that-never-forgets-non-volatile-dimms-hit-the-market/|magazine=[[Ars Technica]]|url-status=live|archive-url=https://web.archive.org/web/20170708073138/https://arstechnica.com/information-technology/2013/04/memory-that-never-forgets-non-volatile-dimms-hit-the-market/|archive-date=July 8, 2017|date=April 4, 2013}}</ref> and other types of [[Non-volatile memory|non-volatile memories]] allow random access for read operations, but either do not allow write operations or have other kinds of limitations. These include most types of [[ROM]] and [[NOR flash memory]].
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===MOS RAM===
In 1957, Frosch and Derick manufactured the first silicon dioxide field-effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650|url-access=subscription
Integrated bipolar [[static random-access memory]] (SRAM) was invented by Robert H. Norman at [[Fairchild Semiconductor]] in 1963.<ref>{{cite patent
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[[Dynamic random-access memory]] (DRAM) allowed replacement of a 4 or 6-transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor and had to be periodically [[Memory refresh|refreshed]] every few milliseconds before the charge could leak away.
[[Toshiba]]'s Toscal BC-1411 [[electronic calculator]], which was introduced in 1965,<ref>[http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator Toscal BC-1411 calculator]. {{webarchive|url=https://web.archive.org/web/20170729145228/http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator |date=2017-07-29
[[File:Bundesarchiv Bild 183-1989-0406-022, VEB Carl Zeiss Jena, 1-Megabit-Chip.jpg|thumb|right|CMOS 1-[[megabit]] (Mbit) DRAM chip, one of the last models developed by [[VEB Carl Zeiss Jena]], in 1989]]
In 1966, [[Robert Dennard]], while examining the characteristics of MOS technology, found it was capable of building [[capacitor]]s, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, and the MOS transistor could control writing the charge to the capacitor. This led to his development of modern DRAM architecture for which there is a single MOS transistor per capacitor.<ref name="ibm100"/> In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology.<ref name="ibm100" /><ref name="Robert Dennard"/> The first commercial DRAM IC chip was the [[Intel 1103]], which was [[Semiconductor manufacturing process|manufactured]] on an [[10 μm process|8{{nbsp}}μm]] MOS process with a capacity of 1{{nbsp}}[[Kilobit|kbit]], and was released in 1970.<ref name="computerhistory1970"/><ref name="Lojek-1103"/><ref>{{cite web |first=Mary |last=Bellis |url=http://inventors.about.com/library/weekly/aa100898.htm |title=Who Invented the Intel 1103 DRAM Chip? |access-date=2025-03-03 |archive-date=2020-03-14 |archive-url=https://web.archive.org/web/20200314061801/http://inventors.about.com/library/weekly/aa100898.htm |url-status=dead}}</ref>
The earliest DRAMs were often synchronized with the CPU clock and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<ref>{{cite book |author=P. Darche |url=https://books.google.com/books?id=rLC9zQEACAAJ |title=Microprocessor: Prolegomenes - Calculation and Storage Functions - Calculation Models and Computer |year=2020 |isbn=9781786305633 |page=59| publisher=John Wiley & Sons
==Types==
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Usually several memory cells share the same address. For example, a 4 bit "wide" RAM chip has four memory cells for each address. Often the width of the memory and that of the microprocessor are different, for a 32 bit microprocessor, eight 4 bit RAM chips would be needed.
Often more addresses are needed than can be provided by a device. In that case, external multiplexors to the device are used to activate the correct device that is being accessed. RAM is often byte addressable, although it is also possible to make RAM that is word-addressable.<ref>{{cite book |
==Memory hierarchy==
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==Memory wall==
The '''memory wall''' is the growing disparity of speed between CPU and the response time of memory (known as [[memory latency]]) outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries
Another reason for the disparity is the enormous increase in the size of memory since the start of the PC revolution in the 1980s. Originally, PCs contained less than 1 mebibyte of RAM, which often had a response time of 1 CPU clock cycle, meaning that it required 0 wait states. Larger memory units are inherently slower than smaller ones of the same type, simply because it takes longer for signals to traverse a larger circuit. Constructing a memory unit of many gibibytes with a response time of one clock cycle is difficult or impossible.
CPU speed improvements slowed significantly partly due to major physical barriers and partly because
<blockquote>First of all, as chip geometries shrink and clock frequencies rise, the transistor [[leakage current]] increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called [[von Neumann bottleneck]]), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, [[RC time constant#Delay|resistance-capacitance]] (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.</blockquote>
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|rowspan="2" | {{?}}
|rowspan="2" | CMOS
|rowspan="2" | <ref name="
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|64 kbit
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|2,500 nm
|NMOS
|<ref name="
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|{{dts|1981|10}}
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|[[1.5 μm process|1,500 nm]]
|NMOS (HMOS)
|<ref name="
|-
|{{dts|1983|2}}
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|1,200 nm
|CMOS
|<ref name="
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|1987
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|{{?}}
|CMOS
|<ref name="
|-
|{{dts|1987|12}}
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|{{?}}
|rowspan="2" | CMOS
|rowspan="2" | <ref name="
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|1992
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|PMOS
|10 mm<sup>2</sup>
|<ref name="Intel2003">{{cite web |title=Intel: 35 Years of Innovation (1968–2003) |url=https://www.intel.com/Assets/PDF/General/35yrs.pdf |publisher=Intel |year=2003 |access-date=26 June 2019}}</ref><ref name="HC">[http://history-computer.com/ModernComputer/Basis/dram.html ''The DRAM memory of Robert Dennard''] {{Webarchive|url=https://web.archive.org/web/20200801004808/https://history-computer.com/ModernComputer/Basis/dram.html |date=2020-08-01 }} history-computer.com</ref><ref name="Lojek-1103">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |pages=362–363 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA362 |quote=The i1103 was manufactured on a 6-mask silicon-gate P-MOS process with 8 μm minimum features. The resulting product had a 2,400 μm<sup>2</sup> memory cell size, a die size just under 10 mm<sup>2</sup>, and sold for around $21.}}</ref>
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| rowspan="2" |1971
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|CMOS
|{{?}}
| rowspan="2" |<ref name="
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|1993
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|CMOS
|{{?}}
|<ref name="
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|1998
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|CMOS
|{{?}}
|<ref name="
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|{{sort|2001|June 2001}}
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