Serial Peripheral Interface: Difference between revisions

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{{Short description|Synchronous serial communication interface}}

{{POV|date=February 2025}}

{{Cleanup rewrite|[[WP:NOTTEXTBOOK|it reads like a guide or textbook]]|article|date=March 2021}}

{{Infobox connector <!-- NOTE: Not a perfect template match, but good enough for now -->

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| data_style = [[Full-duplex]] [[serial communication|serial]]

| daisy_chain = [[#Daisy chain configuration|Depends]] on devices

| manufacturer = variousVarious

| data_devices = [[#Multidrop configuration|Multidrop]] limited by slave selects. [[#Daisy chain configuration|Daisy chaining]] unlimited.

| data_bit_width = 1 bit (bidirectional)

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| maximum_current = Unspecified

| physical_connector = Unspecified

| design_date = Around early 1980s{{NoteTag|The earliest definitive mention of a "Serial Peripheral Interface" in bitsavers archives of Motorola manuals is from 1983 (see {{slink||Original definition}}). While some sources on the web allege that Motorola introduced SPI when 68000 was introduced in 1979, however many of those appear to be [[citogenesis]] or speculation, and Motorola's 1983 68000 manual has no mention of "Serial Peripheral Interface", so the alleged 1979 date doesn'tdoes not seem to be reliable information. Please only add a specific design_date if you have a definitive source from Motorola around then.}}

}}

'''Serial Peripheral Interface''' ('''SPI''') is a <!--DO NOT ITALICIZE; CONSIDERED ANGLICIZED-->[[de facto standard]] (with many [[#Variations|variants]]) for [[Comparison of synchronous and asynchronous signalling|synchronous]] [[serial communication]], used primarily in [[embedded systems]] for short-distance [[wired communication]] between [[integrated circuits]].

SPI follows a [[master–slave (technology)|master–slave architecture]],<ref name=":0">{{Cite web |last=Stoicescu |first=Alin |date=2018 |title=Getting Started with SPI |url=https://ww1.microchip.com/downloads/en/Appnotes/TB3215-Getting-Started-with-SPI-90003215A.pdf |url-status=live |website=[[Microchip]]}}</ref> where a master device [[Signaling (telecommunications)|orchestrates communication]] with one or more slave devices by driving the [[clock signal|clock]] and [[chip select]] signals. Some devices support changing master and slave roles on the fly.

[[Motorola]]'s original specification (from the early 1980s) uses four [[logic signal]]s, aka lines or wires, to support [[full duplex]] communication. It is sometimes called a ''four-wire'' [[serial bus]] to contrast with [[Serial Peripheral Interface#Three-wire|three-wire]] variants which are [[half duplex]], and with the ''two-wire'' [[I²C]] and [[1-Wire]] serial buses.

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===Data transmission===

[[File:SPI 8-bit circular transfer.svg|upright=1.8|thumb|A typical hardware setup using two [[shift register]]s to form an inter-chip [[circular buffer]] ]]

To begin communication, the SPI master first selects a slave device by pulling its {{Overline|SS}} low. (Note: theThe bar above {{Overline|SS}} indicates it is an [[active low]] signal, so a low voltage means "selected", while a high voltage means "not selected")

If a waiting period is required, such as for an analog-to-digital conversion, the master must wait for at least that period of time before issuing clock cycles.{{NoteTag|Some slaves require a falling edge of the {{Overline|Slave Select}} signal to initiate an action. An example is the Maxim MAX1242 ADC, which starts conversion on a high→low transition.}}

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If a single slave device is used, its {{Overline|SS}} pin ''may'' be fixed to [[logic level|logic low]] if the slave permits it. With multiple slave devices, a [[#Multidrop configuration|multidrop configuration]] requires an independent {{Overline|SS}} signal from the master for each slave device, while a [[#Daisy chain configuration|daisy-chain configuration]] only requires one {{Overline|SS}} signal.

Every slave on the bus that has not been selected should disregard the input clock and MOSI signals. And to prevent [[Bus contention|contention]] on MISO, non-selected slaves must use [[Three-state logic|tristate]] output. Slaves that aren'tare not already tristate will need external tristate buffers to ensure this.<ref name="Better SPI Bus Design in 3 Steps" />

===Clock polarity and phase===

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*** Sampling occurs when SCLK transitions ''to'' its idle voltage level.

** Conversion between these two phases is non-trivial.

** Note: MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next bit's transmission cycle starts, so SPI master and slave devices may sample data at different points in that half cycle, for flexibility, despite the original specification.

===Mode numbers ===

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===Interrupts===

Interrupts are outside the scope of SPI; their usage is neither forbidden nor specified, and so may optionally be implemented optionally.

==== From master to slave ====

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** Uses only four pins on IC packages, and wires in board layouts or connectors, much fewer than [[Parallel communication|parallel interfaces]]

*** At most one unique signal per device ({{Overline|SS}}); all others are shared

**** Note: theThe daisy-chain configuration doesn'tdoes not need more than one shared {{Overline|SS}}

** Typically lower power requirements than [[I²C]] or SMBus due to less circuitry (including pull up resistors)

** Single master means no [[bus arbitration]] (and associated failure modes) - unlike [[CAN-bus]]

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* Control devices: [[audio codec]]s, [[digital potentiometers]], [[digital-to-analog converter|DACs]]

* Camera lenses: [[Canon EF lens mount]]

* Communications: [[Ethernet]], [[USB]], [[USART]], [[CAN bus|CAN]], [[IEEE 802.15.4]], [[IEEE 802.11]]

* Memory: [[flash memory#Serial flash|flash]] and [[EEPROM#Serial bus devices|EEPROMs]]

* [[Real-time clock|Real-time clocks]]

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=== No slave select ===

Some devices don'tdo not use slave select, and instead manage protocol state machine entry/exit using other methods.

=== Connectors ===

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=== SafeSPI ===

SafeSPI<ref>[http://SafeSPI.org SafeSPI.org]</ref> is an high industry standard for SPI in automotive applications. Its main focus is the transmission of sensor data between different devices.

=== High reliability modifications ===

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A '''Queued Serial Peripheral Interface''' ('''QSPI'''; different to but has same abbreviation as ''Quad SPI'' described in {{Slink|2=Quad SPI|nopage=y}}) is a type of SPI controller that uses a [[queue (data structure)|data queue]] to transfer data across an SPI bus.<ref>{{Cite web |date=1996 |orig-date=1991 |title=Freescale Semiconductor, Inc. - QSM - Queued Serial Module - Reference Manual |url=https://www.nxp.com/docs/en/reference-manual/QSMRM.pdf |url-status=dead |archive-url=https://web.archive.org/web/20190824080750/https://www.nxp.com/docs/en/reference-manual/QSMRM.pdf |archive-date=2019-08-24 |website=[[NXP]]}}</ref> It has a [[circular buffer|wrap-around]] mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU. Consequently, the peripherals appear to the CPU as [[virtual memory|memory-mapped]] parallel devices. This feature is useful in applications such as control of an [[analog-to-digital converter|A/D converter]]. Other programmable features in Queued SPI are chip selects and transfer length/delay.

SPI controllers from different vendors support different feature sets; such [[direct memory access]] (DMA) queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by '''Multichannel Buffered Serial Port''' ('''MCBSP''').{{NoteTag|Such as with the MultiChannel Serial Port Interface, or McSPI, used in Texas Instruments OMAP chips. (https://www.ti.com/product/OMAP3530)}} Most SPI master controllers integrate support for up to four slave selects,{{NoteTag|Such as the SPI controller on Atmel AT91 chips fanatec like the at91sam9G20, which is much simpler than TI's McSPI.}} although some require slave selects to be managed separately through GPIO lines.

Note that ''Queued SPI'' is different from ''Quad SPI'', and some processors even confusingly allow a single "QSPI" interface to operate in either quad or queued mode!<ref>{{Cite web |date=2023-01-11 |title=Quad-SPI Brings Fast Parallel Data Transmission |url=https://resources.pcb.cadence.com/blog/quad-spi-brings-fast-parallel-data-transmission |url-status=live |archive-url=https://web.archive.org/web/20230601194620/https://resources.pcb.cadence.com/blog/quad-spi-brings-fast-parallel-data-transmission |archive-date=2023-06-01 |access-date=2023-06-30 |website=[[Cadence Design Systems]] |language=en-US}}</ref>