Content deleted Content added
| (4 intermediate revisions by 4 users not shown) | |||
Line 28:
'''Serial Peripheral Interface''' ('''SPI''') is a <!--DO NOT ITALICIZE; CONSIDERED ANGLICIZED-->[[de facto standard]] (with many [[#Variations|variants]]) for [[Comparison of synchronous and asynchronous signalling|synchronous]] [[serial communication]], used primarily in [[embedded systems]] for short-distance [[wired communication]] between [[integrated circuits]].
SPI follows a [[master–slave (technology)|master–slave architecture]],<ref name=":0">{{Cite web |last=Stoicescu |first=Alin |date=2018 |title=Getting Started with SPI |url=https://ww1.microchip.com/downloads/en/Appnotes/TB3215-Getting-Started-with-SPI-90003215A.pdf
[[Motorola]]'s original specification (from the early 1980s) uses four [[logic signal]]s, aka lines or wires, to support [[full duplex]] communication. It is sometimes called a ''four-wire'' [[serial bus]] to contrast with [[Serial Peripheral Interface#Three-wire|three-wire]] variants which are [[half duplex]], and with the ''two-wire'' [[I²C]] and [[1-Wire]] serial buses.
Line 272:
=== SafeSPI ===
SafeSPI<ref>[http://SafeSPI.org SafeSPI.org]</ref> is an high industry standard for SPI in automotive applications. Its main focus is the transmission of sensor data between different devices.
=== High reliability modifications ===
Line 280:
A '''Queued Serial Peripheral Interface''' ('''QSPI'''; different to but has same abbreviation as ''Quad SPI'' described in {{Slink|2=Quad SPI|nopage=y}}) is a type of SPI controller that uses a [[queue (data structure)|data queue]] to transfer data across an SPI bus.<ref>{{Cite web |date=1996 |orig-date=1991 |title=Freescale Semiconductor, Inc. - QSM - Queued Serial Module - Reference Manual |url=https://www.nxp.com/docs/en/reference-manual/QSMRM.pdf |url-status=dead |archive-url=https://web.archive.org/web/20190824080750/https://www.nxp.com/docs/en/reference-manual/QSMRM.pdf |archive-date=2019-08-24 |website=[[NXP]]}}</ref> It has a [[circular buffer|wrap-around]] mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU. Consequently, the peripherals appear to the CPU as [[virtual memory|memory-mapped]] parallel devices. This feature is useful in applications such as control of an [[analog-to-digital converter|A/D converter]]. Other programmable features in Queued SPI are chip selects and transfer length/delay.
SPI controllers from different vendors support different feature sets; such [[direct memory access]] (DMA) queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself, such as used by '''Multichannel Buffered Serial Port''' ('''MCBSP''').{{NoteTag|Such as with the MultiChannel Serial Port Interface, or McSPI, used in Texas Instruments OMAP chips. (https://www.ti.com/product/OMAP3530)}} Most SPI master controllers integrate support for up to four slave selects,{{NoteTag|Such as the SPI controller on Atmel AT91 chips fanatec like the at91sam9G20, which is much simpler than TI's McSPI.}} although some require slave selects to be managed separately through GPIO lines.
Note that ''Queued SPI'' is different from ''Quad SPI'', and some processors even confusingly allow a single "QSPI" interface to operate in either quad or queued mode!<ref>{{Cite web |date=2023-01-11 |title=Quad-SPI Brings Fast Parallel Data Transmission |url=https://resources.pcb.cadence.com/blog/quad-spi-brings-fast-parallel-data-transmission |url-status=live |archive-url=https://web.archive.org/web/20230601194620/https://resources.pcb.cadence.com/blog/quad-spi-brings-fast-parallel-data-transmission |archive-date=2023-06-01 |access-date=2023-06-30 |website=[[Cadence Design Systems]] |language=en-US}}</ref>
| |||