Bit manipulation instructions: Difference between revisions

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{{primary sources|date=August 2025}}

{{Short description|Hardware-level Bit manipulation instructions}}

{{About|the general topic of Instruction set bit manipulation subsets|bit manipulation extensions unique to AMD and Intel|x86 Bit manipulation instruction set}}

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'''Bit manipulation instructions''' are [[instruction set architecture|instructions]] that perform [[bit manipulation]] operations in hardware, rather than requiring several instructions for those operations as illustrated with [[Bit manipulation#Example of bit manipulation|examples in software]].<ref>{{cite web | title=Bit Twiddling Hacks | url=https://graphics.stanford.edu/~seander/bithacks.html}}</ref> Several leading as well as historic architectures have bit manipulation instructions including [[ARM]], [[WDC 65C02]], the [[TX-2]] and the [[Power ISA]].<ref>{{cite web | title=Advanced bit manipulation instructions: Architecture, implementation and applications | website=[[ProQuest]] | url=https://www.proquest.com/openview/0ad3a2474b0691b65b35582fbdb3cf40/1?pq-origsite=gscholar&cbl=18750 }}</ref>

Bit manipulation is usually divided into subsets as individual instructions can be costly to implement in hardware when the target application has no justification. Conversely, if there ''is'' a justification then performance may suffer if the instruction is excluded. Carrying out the cost-benefit analysis is a complex task: one of the most comprehensive efforts in bit manipulation was a collaboration headed by Clare Wolfe, providing justifications, use-cases, c code, proofs and Verilog for each proposed RISC-V instruction.<ref>{{cite web | title=GitHub - riscv/Riscv-bitmanip at v0.93 | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/tree/v0.93 }}</ref><ref>https://raw.githubusercontent.com/riscv/riscv-bitmanip/master/bitmanip-draft.pdf {{Bare URL PDF|date=August 2025}}</ref>

Particular practical examples include [[Bit banging]] of [[GPIO]] using a low-cost [[Embedded controller]] such as the [[WDC 65C02]], [[8051]] and [[PIC instruction listings#Baseline core devices (12-bit)|Atmel PIC]]. At the slow clock rate of these CPUs, if bit-set/clear/test bit manipulation were not available the use of that low-cost CPU would, self-evidently, not be viable for the target application.

<!-- {{WTMM-note|

In something of a Wikipedia [[Fourth wall]] breakage note: [[GPUs]] and other highly-specialist tasks such as cryptography tend to result in extreme-specialist instructions, wthout which performance would suck. Examples include [[AES instruction set]] extensions that cannot in any way be used for any other purpose. GPUs such as Larrabee<ref>{{cite web | title=TomF's talks and papers | url=https://tomforsyth1000.github.io/papers/papers.html }}</ref> and [[Single instruction, multiple threads#Nyuzi GPGPU|Nyuzi]] attempted to "dial back" this practice to some extent, only to discover why it is done (performance sucks otherwise... seeing a trend, here?).

This page is ''not'' about such specialised instructions, nor even of their functionality. It covers useful ''Categorisation'' of the ''existence'' in CPUs and CPU families, of ''general-purpose'' bit-manipulation instructions that ''happen'' to greatly improve performance or power consumption of specific algorithms. An example is cryptography making heavy use of [[Bitwise operation#Rotate|rotate]], but rotate having many other practical uses elsewhere: just not as many as, say, Add, which results in rotate being optional where Add does not. Such ISA design trade-offs are notoriously meticulous but ultimately pragmatic.

If you encounter any type of ''unusual or important'' bit manipulation instructions, or any CPU that has them, feel free to add them below, bearing in mind that the page's primary purpose is Categorisation, not explicit functional description per se. A helpful task for future readers would be to add such pages describing the functionality to the "See also" section. Enjoy the end of the Fourth Wall...

}}-->

== Hardware bit manipulation ==

{{Further|topic=categorisation of all types of bit and bitwise manipulation|Bit_manipulation#Bit_manipulation_operations}}

{{Further|topic=a more complete list of find-first style instructions|Find_first_set#Hardware_support}}

All the architectures below have instruction subsets and groups where the bit manipulation is provided in hardware. From the list it can be seen that [[DSP]]s and [[Embedded system|Embedded]] [[Microcontroller]]s have at least test/set/clear bit, however there are much more comprehensive instructions such as [[Count leading zeros]], [[Popcount]], [[Galois field]] arithmetic, [[Binary-coded decimal]], bit-matrix multiply and transpose, byte-permute, bit permute including [[Bit-reversal_permutation|bit-reversal]], specialised cryptographic instructions and many more.

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=== Intel and AMD (x86) ===

* The x86 instruction core set contains:

** {{code|BSR}} Bit Scan Reverse - aReturns quirkybit index of highest set bit in input, effectively backwards count leading zeros, not defined for 0.

** {{code|BSF}} Bit Scan Forward - aReturns quirkybit backwardsindex of lowest set bit in input, effectively count trailing zeros, but not defined for 0.

* [[SSE4]] and the [[X86 Bit manipulation instruction set|BMI]] instruction set extensions contains instructions for:

** Count leading zeros - {{code|lzcnt}},

** Count trailing zeros - {{code|tzcnt}}

** Population count - {{code|popcnt}}

** Bit extract/bit deposit - {{code|pext}}/{{code|pdep}}

** Bit test - {{code|PTESTptest}} and {{code|vptest}}, given two inputs, doesdo aboth an {{code|AND}} operation and an {{code|ANDN}} operation between them, and setsset twothe separateZF CPUand branchCF registersEFLAGS bits on wetherwhether the results of the AND and ANDN, respectively, are 0. This can be used to test if all masked bits are zero, all masked bits are set, or a mix.

* The [[AVX-512#Bitwise ternary logic|AVX-512 ternary]] extension includes a [[Bitwise ternary logic instruction]], {{code|vpternlog}}. Also noteworthy is a conflict detection instruction. [[AVX-512#Conflict detection|<code>VPCONFLICTD</code>]]

* Also present in the AVX/[[AVX-512]] [[GFNI instruction set|GFNI subset]] is bit-matrix affine transformation and its inverse: {{code|GF2P8AFFINEQB}} is effectively an 8x8 bit-matrix multiply in the [[Galois field]] GF(2^8).<ref>{{cite web | title=GF2P8AFFINEQB — Galois Field Affine Transformation | url=https://www.felixcloutier.com/x86/gf2p8affineqb }}</ref>

* AVX-512 BITALG besides AVX-512 version of existing bit manipulation instruction, also added {{code|VPSHUFBITQMB}} which is a bit-level shuffle instruction, that picks bits from one source using indexes in the second source.

* An Intel GNFI technology guide on that AVX/AVX512 GNFI Extension also lists numerous uses including parallel byte-wise set/clear/invert bitmanipulation, 5-bit sign-extension and points out the potential is much greater.<ref name=gfni>{{cite web |title=Galois Field New Instructions (GFNI) Technology Guide |url=https://networkbuilders.intel.com/solutionslibrary/galois-field-new-instructions-gfni-technology-guide |website=networkbuilders.intel.com |language=en}}</ref>

* [[Intel BCD opcodes]]

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Later models of the PDP-10 had instructions to convert between [[Binary-coded decimal#Packed BCD|packed BCD]] and binary.{{sfn|pdp10|pages=2{{hyp}}99|}}

Also present is unusual (variable-bit-length) byte load and store instructions that use ''byte pointers'' for memory operands: in modern terminology these are bit-field insert and extract. In addition to a word address, the bit length (S) and the bit offset (P) of the byte from which to load or into which to store are specified. These instructions can specify a byte size of 0-36, but a byte may not straddle a word boundary.{{sfn|pdp10|pages=2{{hyp}}85-2{{hyp}}89|loc=Byte manipulation|}} The string manipulation,{{sfn|pdp10|pages=2{{hyp}}91-2{{hyp}}99|loc=2.12 String Manipulation|}} BCD/binary conversion,{{sfn|pdp10|pages=2{{hyp}}98-2{{hyp}}103|loc=2.13 Decimal Conversion|}} and string editing{{sfn|pdp10|pages=2{{hyp}}104-2{{hyp}}112|loc=2.14 String Editing|}} instructions in later models use byte pointers and have the same restrictions.

===GE-600 series===

The [[GE-600 series]] and its successors had Gray-to-binary conversion; without such an instruction, [[Gray code#Converting to and from Gray code|converting from Gray code]] requires multiple steps. Binary-to-Gray is simply {{code|x^(x>>1)}} and does not justify a dedicated instruction. Gray coding has significant [[Gray code#History and practical application|practical applications]].

=== ARM ===

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=== RISC-V ===

In the standard extensions RISC-V has scalar [[bitwise operations]] including shift and arithmetic shift, but no rotate. The omissions are compensated for with additional extensions.

* [[RISC-V]] Zb* extensions contain a significant number of bit manipulation instructions.<ref>{{cite web | title=Riscv-bitmanip/Bitmanip/Index.adoc at main · riscv/Riscv-bitmanip | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/index.adoc }}</ref> The four groups are broken down into useful categories (the integer subset has min/max, rotate and [[Popcount]] for example), and have very good well-researched justifications for their inclusion and the improvements they bring.<ref>{{cite web | title=Riscv-bitmanip/Bitmanip/Overview.adoc at main · riscv/Riscv-bitmanip | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/overview.adoc }}</ref>

* The RISC-V Vector Extension (RVV) has instructions that qualify as hardware-level bit manipulation, but on Vector masks rather than Scalar registers as is normally the case. For example, a Vector-mask [[Popcount]] is available.<ref>{{cite web | title=Riscv-v-spec/V-spec.adoc at master · riscvarchive/Riscv-v-spec | website=[[GitHub]] | url=https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#15-vector-mask-instructions }}</ref> RVV also has per-element [[bitwise operations]].<ref>{{cite web | title=Riscv-v-spec/V-spec.adoc at master · riscvarchive/Riscv-v-spec | website=[[GitHub]] | url=https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#115-vector-bitwise-logical-instructions }}</ref>

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==== Zilog Z80 ====

* The [[Zilog Z80]] [[Z80 instruction set|instruction set]] includes {{code|BIT}}, {{code|RES}}, and {{code|SET}} instructions. These test, reset, and set individual bits in registers or memory pointed to by HL.<ref>{{Cite book |url=https://www.zilog.com/docs/z80/um0080.pdf#G5.1130345 |title=Z80 Family CPU User Manual |publisher=[[Zilog]] |year=2016 |id=UM008011-0816 |access-date=January 5, 2024 |archive-url=https://web.archive.org/web/20231226131929/http://www.zilog.com/docs/z80/um0080.pdf#G5.1130345 |archive-date=December 26, 2023 |url-status=live}}</ref>

==== MOS 6502 ====

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* [[SuperH]] has comprehensive memory-based bit manipulation including And-complement and Or-complement, but also has standard register-based test/set/clear and an unusual instruction that replaces bit N (in the range 0 to 7) and copies the replaced bit into the Test register.<ref>{{cite web | title=Renesas SH Instruction Set Summary | url=https://shared-ptr.com/sh_insns.html }}</ref>

* The [[Signetics]] [[Signetics 8X300|8X300]] is a microprocessor produced starting 1976. The processor normally manipulates 8-bit data bytes, but the mask and rotate units makes it possible to manipulate single or multiple bits, making this a variable data-length processor.

== Notes ==

{{notelist}}

== See also ==

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}}

{{Reflist}}

== Further reading ==

* {{cite thesis |last1=Hilewitz |first1=Yedidya |title=Advanced bit manipulation instructions: Architecture, implementation and applications |date=2008 |publisher=[[Princeton University]] |degree=PhD |url=https://www.proquest.com/openview/0ad3a2474b0691b65b35582fbdb3cf40/1.pdf?pq-origsite=gscholar&cbl=18750}}

** {{cite book |last1=Hilewitz |first1=Yedidya |last2=Lee |first2=Ruby B. |title=Advanced Bit Manipulation Instruction Set Architecture. Technical Report CE-L2006-004 |date=November 2006 |publisher=Princeton University Department of Electrical Engineering |url=https://www.researchgate.net/publication/249884287}}

* {{cite conference |last1=Koppelmann |first1=Bastian |last2=Adelt |first2=Peer |last3=Mueller |first3=Wolfgang |last4=Scheytt |first4=Christoph |conference=2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) |title=RISC-V Extensions for Bit Manipulation Instructions |publisher=IEEE |date=2019 |pages=41–48 |isbn=978-1-7281-2103-1 |doi=10.1109/PATMOS.2019.8862170 }}

{{Instruction set extensions}}