Bit manipulation instructions: Difference between revisions

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{{primary sources|date=August 2025}}

{{Short description|Hardware-level Bit manipulation instructions}}

{{About|the general topic of Instruction set bit manipulation subsets|bit manipulation extensions unique to AMD and Intel|x86 Bit manipulation instruction set}}

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Particular practical examples include [[Bit banging]] of [[GPIO]] using a low-cost [[Embedded controller]] such as the [[WDC 65C02]], [[8051]] and [[PIC instruction listings#Baseline core devices (12-bit)|Atmel PIC]]. At the slow clock rate of these CPUs, if bit-set/clear/test bit manipulation were not available the use of that low-cost CPU would, self-evidently, not be viable for the target application.

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In something of a Wikipedia [[Fourth wall]] breakage note: [[GPUs]] and other highly-specialist tasks such as cryptography tend to result in extreme-specialist instructions, wthout which performance would suck. Examples include [[AES instruction set]] extensions that cannot in any way be used for any other purpose. GPUs such as Larrabee<ref>{{cite web | title=TomF's talks and papers | url=https://tomforsyth1000.github.io/papers/papers.html }}</ref> and [[Single instruction, multiple threads#Nyuzi GPGPU|Nyuzi]] attempted to "dial back" this practice to some extent, only to discover why it is done (performance sucks otherwise... seeing a trend, here?).

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If you encounter any type of ''unusual or important'' bit manipulation instructions, or any CPU that has them, feel free to add them below, bearing in mind that the page's primary purpose is Categorisation, not explicit functional description per se. A helpful task for future readers would be to add such pages describing the functionality to the "See also" section. Enjoy the end of the Fourth Wall...

}}-->

== Hardware bit manipulation ==

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=== Intel and AMD (x86) ===

* The x86 instruction core set contains:

** {{code|BSR}} Bit Scan Reverse - aReturns quirkybit index of highest set bit in input, effectively backwards count leading zeros, not defined for 0.

** {{code|BSF}} Bit Scan Forward - aReturns quirkybit backwardsindex of lowest set bit in input, effectively count trailing zeros, but not defined for 0.

* [[SSE4]] and the [[X86 Bit manipulation instruction set|BMI]] instruction set extensions contains instructions for:

** Count leading zeros - {{code|lzcnt}}

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* The [[AVX-512#Bitwise ternary logic|AVX-512 ternary]] extension includes a [[Bitwise ternary logic instruction]], {{code|vpternlog}}. Also noteworthy is a conflict detection instruction. [[AVX-512#Conflict detection|<code>VPCONFLICTD</code>]]

* Also present in the AVX/[[AVX-512]] [[GFNI instruction set|GFNI subset]] is bit-matrix affine transformation and its inverse: {{code|GF2P8AFFINEQB}} is effectively an 8x8 bit-matrix multiply in the [[Galois field]] GF(2^8).<ref>{{cite web | title=GF2P8AFFINEQB — Galois Field Affine Transformation | url=https://www.felixcloutier.com/x86/gf2p8affineqb }}</ref>

* AVX-512 BITALG besides AVX-512 version of existing bit manipulation instruction, also added {{code|VPSHUFBITQMB}} which is a bit-level shuffle instruction, that picks bits from one source using indexes in the second source.

* An Intel GNFI technology guide on that AVX/AVX512 GNFI Extension also lists numerous uses including parallel byte-wise set/clear/invert bitmanipulation, 5-bit sign-extension and points out the potential is much greater.<ref name=gfni>{{cite web |title=Galois Field New Instructions (GFNI) Technology Guide |url=https://networkbuilders.intel.com/solutionslibrary/galois-field-new-instructions-gfni-technology-guide |website=networkbuilders.intel.com |language=en}}</ref>

* [[Intel BCD opcodes]]

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=== RISC-V ===

In the standard extensions RISC-V has scalar [[bitwise operations]] including shift and arithmetic shift, but no rotate. The omissions are compensated for with additional extensions.

* [[RISC-V]] Zb* extensions contain a significant number of bit manipulation instructions.<ref>{{cite web | title=Riscv-bitmanip/Bitmanip/Index.adoc at main · riscv/Riscv-bitmanip | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/index.adoc }}</ref> The four groups are broken down into useful categories (the integer subset has min/max, rotate and [[Popcount]] for example), and have very good well-researched justifications for their inclusion and the improvements they bring.<ref>{{cite web | title=Riscv-bitmanip/Bitmanip/Overview.adoc at main · riscv/Riscv-bitmanip | website=[[GitHub]] | url=https://github.com/riscv/riscv-bitmanip/blob/main/bitmanip/overview.adoc }}</ref>

* The RISC-V Vector Extension (RVV) has instructions that qualify as hardware-level bit manipulation, but on Vector masks rather than Scalar registers as is normally the case. For example, a Vector-mask [[Popcount]] is available.<ref>{{cite web | title=Riscv-v-spec/V-spec.adoc at master · riscvarchive/Riscv-v-spec | website=[[GitHub]] | url=https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#15-vector-mask-instructions }}</ref> RVV also has per-element [[bitwise operations]].<ref>{{cite web | title=Riscv-v-spec/V-spec.adoc at master · riscvarchive/Riscv-v-spec | website=[[GitHub]] | url=https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#115-vector-bitwise-logical-instructions }}</ref>

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==== Zilog Z80 ====

* The [[Zilog Z80]] [[Z80 instruction set|instruction set]] includes {{code|BIT}}, {{code|RES}}, and {{code|SET}} instructions. These test, reset, and set individual bits in registers or memory pointed to by HL.<ref>{{Cite book |url=https://www.zilog.com/docs/z80/um0080.pdf#G5.1130345 |title=Z80 Family CPU User Manual |publisher=[[Zilog]] |year=2016 |id=UM008011-0816 |access-date=January 5, 2024 |archive-url=https://web.archive.org/web/20231226131929/http://www.zilog.com/docs/z80/um0080.pdf#G5.1130345 |archive-date=December 26, 2023 |url-status=live}}</ref>

==== MOS 6502 ====

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{{Reflist}}

== Further reading ==

* {{cite thesis |last1=Hilewitz |first1=Yedidya |title=Advanced bit manipulation instructions: Architecture, implementation and applications |date=2008 |publisher=[[Princeton University]] |degree=PhD |url=https://www.proquest.com/openview/0ad3a2474b0691b65b35582fbdb3cf40/1.pdf?pq-origsite=gscholar&cbl=18750}}

** {{cite book |last1=Hilewitz |first1=Yedidya |last2=Lee |first2=Ruby B. |title=Advanced Bit Manipulation Instruction Set Architecture. Technical Report CE-L2006-004 |date=November 2006 |publisher=Princeton University Department of Electrical Engineering |url=https://www.researchgate.net/publication/249884287}}

* {{cite conference |last1=Koppelmann |first1=Bastian |last2=Adelt |first2=Peer |last3=Mueller |first3=Wolfgang |last4=Scheytt |first4=Christoph |conference=2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) |title=RISC-V Extensions for Bit Manipulation Instructions |publisher=IEEE |date=2019 |pages=41–48 |isbn=978-1-7281-2103-1 |doi=10.1109/PATMOS.2019.8862170 }}

{{Instruction set extensions}}