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#REDIRECT [[System bus]]
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|concern = The topic is not notable. Searching Google Books for the terms "system bus model" and "von Neumann" (to prevent the return of irrelevant results discussing system bus models in the context of simulation) returns three results. Searching Google Scholar returns two. Of the three Google Books results, two are textbooks with trivial mentions of the topic, and the other is a mirror of this article. Of the two Google Scholar Results, one is the same textbook found in Google Books, and the other is what appears to be some university's internal teaching material.
|timestamp = 20101018031626
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{{Orphan|date=February 2009}}
[[Image:Systembusmodel.png|thumb|right|400px]]
The '''system bus model''' is a streamlined version of the [[Von Neumann architecture|Von Neumann model]] of computer architecture. The system bus models divides the computer into three individual subunits which are the CPU, memory and input/output. The system bus model deviates from the von Neumann model by combining the [[arithmetic logic unit]] (ALU) and the [[central processing unit]] (CPU) into a single unit.<ref name="POCA">{{cite book|first=Miles J.|last=Murdocca| coauthors=Vincent P. Heuring|year=2000|title=Principles of Computer Architecture|publisher=Prentice-Hall|id=ISBN 0-201-43664-7|pages=5}}</ref>
==Communications==
A key feature of the System bus model are the shared communication pathways all part of the system bus.<ref name="POCA"/>
The system bus is composed of the data bus, address bus, control bus, power bus and sometimes an I/O bus.<ref name="POCA"/>
The data bus is used for transfer of data between subunits while the address bus is used to transmit ___location information between units such as where the data is going or coming from.<ref name="POCA"/>
The control bus is used to provide information as to how data is being sent.<ref name="POCA"/>
The power bus is often not graphically depicted on models but is understood to exist. Furthermore, some more complex architectures may also incorporate a separate I/O bus for transfer of data between Input/Output devices.<ref name="POCA"/>
==References==
{{reflist}}
[[Category:Computer architecture]]
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