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#REDIRECT [[System bus]]
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{{Article for deletion/dated|page=System bus model|timestamp=20110430064033|year=2011|month=April|day=30|substed=yes}}
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{{Orphan|date=February 2009}}
{{merge to|Von Neumann architecture|discuss=Talk:System bus model#PROD|date=October 2010}}
[[Image:Systembusmodel.png|thumb|right|400px]]
The '''system bus model''' is a streamlined version of the [[Von Neumann architecture|von Neumann model]] of computer architecture.<ref>{{cite book |title=The essentials of computer organization and architecture |author1=Linda Null |author2=Julia Lobur |publisher=Jones & Bartlett Learning |year=2006 |isbn=9780763737696 |edition=2}}</ref> The system bus models divides the computer into three individual subunits which are the CPU, memory and input/output. The system bus model deviates from the von Neumann model by combining the [[arithmetic logic unit]] (ALU) and the [[central processing unit]] (CPU) into a single unit.<ref name="POCA">{{cite book|first=Miles J.|last=Murdocca| coauthors=Vincent P. Heuring|year=2000|title=Principles of Computer Architecture|publisher=Prentice-Hall|id=ISBN 0-201-43664-7|pages=5}}</ref>
==Communications==
A key feature of the system bus model is that the shared communication pathways are all part of the system bus.<ref name="POCA"/>
The system bus is composed of the data bus, address bus, control bus, power bus and sometimes an I/O bus.<ref name="POCA"/>
The data bus is used for transfer of data between subunits while the address bus is used to transmit ___location information between units such as where the data is going or coming from.<ref name="POCA"/>
The control bus is used to provide information as to how data is being sent.<ref name="POCA"/>
The power bus is often not graphically depicted on models but is understood to exist. Furthermore, some more complex architectures may also incorporate a separate I/O bus for transfer of data between input/output devices.<ref name="POCA"/>
==References==
{{reflist}}
{{DEFAULTSORT:System Bus Model}}
[[Category:Computer architecture]]
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