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{{outdated|date=January 2014}}
{{short description|Processor interconnect developed by Intel}}
The '''Intel QuickPath Interconnect''' ('''QPI''')<ref name="Intel QPI">{{cite web |title= An Introduction to the Intel QuickPath Interconnect |date= January 30, 2009 |publisher= Intel Corporation |url= http://www.intel.com/technology/quickpath/introduction.pdf |access-date= June 14, 2011 }}</ref><ref>[http://www.dailytech.com/SMT+Multilevel+Cache+Confirmed+for+Nehalem/article8082.htm DailyTech report] {{webarchive|url=https://web.archive.org/web/20131017230331/http://www.dailytech.com/SMT+Multilevel+Cache+Confirmed+for+Nehalem/article8082.htm |date=2013-10-17 }}, retrieved August 21, 2007</ref> is a point-to-point [[microprocessor|processor]] [[electrical connection|interconnect]] developed by [[Intel]] which replaced the [[front-side bus]] (FSB) in [[Xeon]], [[Itanium]], and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth. Prior to the name's announcement, Intel referred to it as '''Common System Interface''' ('''CSI''').<ref>{{Cite news |title= Intel CSI name revealed: Slow, slow, quick quick slow |work= The Inquirer |author= Eva Glass |date= May 16, 2007 |url= http://www.theinquirer.net/inquirer/news/1016558/intel-csi-revealed |access-date= September 13, 2013 }}</ref> Earlier incarnations were known as Yet Another Protocol (YAP) and YAP+.▼
{{Redirect|QPI||Quasiparticle interference imaging}}
▲The '''Intel QuickPath Interconnect''' ('''QPI''')<ref name="Intel QPI">{{cite web |title= An Introduction to the Intel QuickPath Interconnect |date= January 30, 2009 |publisher= Intel Corporation |url= http://www.intel.com/technology/quickpath/introduction.pdf |access-date= June 14, 2011 }}</ref><ref>[http://www.dailytech.com/SMT+Multilevel+Cache+Confirmed+for+Nehalem/article8082.htm DailyTech report] {{webarchive|url=https://web.archive.org/web/20131017230331/http://www.dailytech.com/SMT+Multilevel+Cache+Confirmed+for+Nehalem/article8082.htm |date=2013-10-17 }}, retrieved August 21, 2007</ref> is a
QPI 1.1 is a significantly revamped version introduced with [[Sandy Bridge-EP]] ([[Romley]] platform).<ref>{{cite web|author=David Kanter |url=http://www.realworldtech.com/qpi-evolved/ |title=Intel's Quick Path Evolved |publisher=Realworldtech.com |date=2011-07-20 |access-date=2014-01-21}}</ref>
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==Background==
Although sometimes called a "bus", QPI is a
Its development had been reported as early as 2004.<ref>{{Cite news |title= Intel's Whitefield takes four core IA-32 shape |work= The Inquirer |author= Eva Glass |date=December 12, 2004 |url= http://www.theinquirer.net/inquirer/news/1028779/intels--whitefield-takes-four-core-ia-32--shape |archive-url= https://web.archive.org/web/20090524173105/http://www.theinquirer.net/inquirer/news/1028779/intels--whitefield-takes-four-core-ia-32--shape |url-status= unfit |archive-date= May 24, 2009 |access-date= September 13, 2013 }}</ref>▼
▲Its development had been reported as early as 2004.<ref>{{Cite news |title= Intel's Whitefield takes four core IA-32 shape |work= The Inquirer |author= Eva Glass |date=December 12, 2004 |url= http://www.theinquirer.net/inquirer/news/1028779/intels--whitefield-takes-four-core-ia-32--shape |access-date= September 13, 2013 }}</ref>
Intel first delivered it for desktop processors in November 2008 on the [[Bloomfield (microprocessor)|Intel Core i7-9xx]] and [[Intel X58|X58]] [[chipset]].
It was released in Xeon processors code-named [[Nehalem (microarchitecture)|Nehalem]] in March 2009 and Itanium processors in February 2010 (code named Tukwila).<ref>{{cite web |title=
It was supplanted by the [[Intel Ultra Path Interconnect]] starting in 2017 on the [[Xeon]] [[Skylake-SP]] platforms. <ref>{{cite web |url=https://www.intel.com/content/www/us/en/developer/articles/technical/xeon-processor-scalable-family-technical-overview.html |title = Intel® Xeon® Processor Scalable Family Technical Overview}}</ref>
==Implementation==
[[File:Intel Nehalem arch.svg|thumb|right|upright=2.2|QPI is an [[uncore]] component in Intel's [[Nehalem (microarchitecture)|Nehalem]] microarchitecture.]]
The QPI is an element of a system architecture that Intel calls the ''QuickPath architecture'' that implements what Intel calls ''QuickPath technology''.<ref>{{cite web |title=Intel Demonstrates Industry's First 32nm Chip and Next-Generation Nehalem Microprocessor Architecture |url= http://www.intel.com/pressroom/archive/releases/20070918corp_a.htm?iid=tech_arch_32nm+body_pressrelease |access-date=2007-12-31 |archive-url=https://web.archive.org/web/20080102101316/http://www.intel.com/pressroom/archive/releases/20070918corp_a.htm?iid=tech_arch_32nm+body_pressrelease |archive-date=2008-01-02}}</ref> In its simplest form on a single-processor motherboard, a single QPI is used to connect the processor to the IO Hub (e.g., to connect an [[Intel Core i7]] to an [[Intel X58|X58]]). In more complex instances of the architecture, separate QPI link pairs connect one or more processors and one or more IO hubs or routing hubs in a network on the motherboard, allowing all of the components to access other components via the network. As with HyperTransport, the QuickPath Architecture assumes that the processors will have integrated [[memory controller]]s, and enables a [[non-uniform memory access]] (NUMA) architecture.
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Each QPI comprises two 20-lane point-to-point data links, one in each direction ([[full duplex]]), with a separate clock pair in each direction, for a total of 42 signals. Each signal is a [[differential signaling|differential pair]], so the total number of pins is 84. The 20 data lanes are divided onto four "quadrants" of 5 lanes each. The basic unit of transfer is the 80-bit [[flit (computer networking)|flit]], which has 8 bits for error detection, 8 bits for "link-layer header", and 64 bits for data. One 80-bit flit is transferred in two clock cycles (four 20-bit transfers, two per clock tick.) QPI bandwidths are advertised by computing the transfer of 64 bits (8 bytes) of data every two clock cycles in each direction.<ref name="realworld">{{cite web |title= The Common System Interface: Intel's Future Interconnect |work= Real World Tech |author= David Kanter |date= August 28, 2007 |url= http://www.realworldtech.com/common-system-interface/ |access-date= August 14, 2014 }}</ref>
Although the initial implementations use single four-quadrant links, the QPI specification permits other implementations. Each quadrant can be used independently. On high-reliability servers, a QPI link can operate in a degraded mode. If one or more of the 20+1 signals fails, the interface will operate using 10+1 or even 5+1 remaining signals, even reassigning the clock to a data signal if the clock fails.<ref name="realworld"/> The initial Nehalem implementation used a full four-quadrant interface<!-- what is that? --> to achieve 25.6 GB/s (6.4GT/s × 1 byte × 4), which provides exactly double the theoretical bandwidth of Intel's 1600 MHz FSB used in the X48 chipset.
Although some high-end Core i7 processors expose QPI, other "mainstream" Nehalem desktop and mobile processors intended for single-socket boards (e.g. [[LGA 1156]] Core i3, Core i5, and other Core i7 processors from the [[Lynnfield (microprocessor)|Lynnfield]]/[[Clarksfield (microprocessor)|Clarksfield]] and successor families) do not expose QPI externally, because these processors are not intended to participate in multi-socket systems.
However, QPI is used internally on these chips to communicate with the "[[uncore]]", which is part of the chip containing memory controllers, CPU-side [[PCI Express]] and GPU, if present; the uncore may or may not be on the same die as the CPU core, for instance it is on a separate die in the [[Westmere (microarchitecture)|Westmere]]-based [[Clarkdale (microprocessor)|Clarkdale]]/[[Arrandale]].<ref>{{cite web|author=Chris Angelini |url=http://www.tomshardware.com/reviews/intel-core-i5,2410-3.html |title=QPI, Integrated Memory, PCI Express, And LGA 1156 - Intel Core i5 And Core i7:
| url = http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.19.9-Desktop-CPUs/HC23.19.911-Sandy-Bridge-Lempel-Intel-Rev%207.pdf
| title = 2nd Generation Intel Core Processor Family: Intel Core i7, i5 and i3
| date = 2013-07-28
| access-date = 2014-01-21 | author = Oded Lempel
| website = hotchips.org |
| archive-url = https://web.archive.org/web/20200729000210/http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.19.9-Desktop-CPUs/HC23.19.911-Sandy-Bridge-Lempel-Intel-Rev%207.pdf
}}</ref>{{rp|3}}▼
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▲ }}</ref>{{rp|3}}
In post-2009 single-socket chips starting with Lynnfield, Clarksfield, Clarkdale and Arrandale, the traditional [[Northbridge (computing)|northbridge]] functions are integrated into these processors,
Thus, there is no need to incur the expense of exposing the (former) front-side bus interface via the processor socket.<ref>Lily Looi, Stephan Jourdan, [http://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.442.Looi-Intel_NhmClient_Hotchips2009b.pdf Transitioning the Intel® Next Generation Microarchitectures (Nehalem and Westmere) into the Mainstream] {{Webarchive|url=https://web.archive.org/web/20200802042642/http://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.442.Looi-Intel_NhmClient_Hotchips2009b.pdf |date=2020-08-02 }}, Hot Chips 21, August 24, 2009</ref>
▲In post-2009 single-socket chips starting with Lynnfield, Clarksfield, Clarkdale and Arrandale, the traditional [[Northbridge (computing)|northbridge]] functions are integrated into these processors, and therefore they communicate externally via the slower [[Direct Media Interface|DMI]] and PCI Express interfaces.
==Frequency specifications==
Being a [[synchronous circuit]] the QPI operates at a clock rate of 2.4 GHz, 2.93 GHz, 3.2 GHz, 3.6 GHz, 4.0 GHz or 4.8 GHz (3.6 GHz and 4.0 GHz frequencies were introduced with the Sandy Bridge-E/EP platform and 4.8 GHz with the Haswell-E/EP platform). The clock rate for a particular link depends on the capabilities of the components at each end of the link and the signal characteristics of the signal path on the printed circuit board. The non-extreme Core i7 9xx processors are restricted to a 2.4 GHz frequency at stock reference clocks.
Bit transfers occur on both the rising and the falling edges of the clock, so the transfer rate is double the clock rate.
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: The transport layer is not needed and is not present in devices that are intended for only point-to-point connections. This includes the Core i7. The transport layer sends and receives data across the QPI network from its peers on other devices that may not be directly connected (i.e., the data may have been routed through an intervening device.) the transport layer verifies that the data is complete, and if not, it requests retransmission from its peer.
; Protocol layer
: The protocol layer sends and receives packets on behalf of the device. A typical packet is a memory cache row. The protocol layer also participates in maintenance of cache
==See also==
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==External links==
* [http://www.intel.com/content/www/us/en/io/quickpath-technology/quick-path-interconnect-introduction-paper.html An Introduction to the Intel QuickPath Interconnect]
* [http://www.hotchips.org/wp-content/uploads/hc_archives/hc21/1_sun/HC21.23.1.SystemInterconnectTutorial-Epub/HC21.23.120.Safranek-Intel-QPI.pdf Intel QuickPath Interconnect Overview] {{Webarchive|url=https://web.archive.org/web/20140202205507/http://www.hotchips.org/wp-content/uploads/hc_archives/hc21/1_sun/HC21.23.1.SystemInterconnectTutorial-Epub/HC21.23.120.Safranek-Intel-QPI.pdf |date=2014-02-02 }} (PDF)
* [https://arstechnica.com/gadgets/2008/04/what-you-need-to-know-about-nehalem/ What you need to know about Intel’s Nehalem CPU], ''[[Ars Technica]]'', April 9, 2008, by Jon Stokes
* [http://www.xbitlabs.com/articles/cpu/display/nehalem-microarchitecture_8.html#sect0 First Look at Nehalem Microarchitecture: QPI Bus] {{Webarchive|url=https://web.archive.org/web/20160514050557/http://www.xbitlabs.com/articles/cpu/display/nehalem-microarchitecture_8.html#sect0 |date=2016-05-14 }}, November 2, 2008, by Ilya Gavrichenkov
* [http://www.realworldtech.com/common-system-interface/ The Common System Interface: Intel’s Future Interconnect], August 28, 2007, by David Kanter
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