Advanced Programmable Interrupt Controller: Difference between revisions

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{{Short description|Family of computer interrupt controllers}}

In [[computing]], [[Intel]]'s '''Advanced Programmable Interrupt Controller''' ('''APIC''') is a family of [[programmable interrupt controller]]s. As its name suggests, the APIC is more advanced than Intel's [[8259]] [[Programmable Interrupt Controller]] (PIC), particularly enabling the construction of [[multiprocessor]] systems. It is one of several architectural designs intended to solve interrupt routing efficiency issues in multiprocessor computer systems.

The APIC is a split architecture design, with a local component (LAPIC) usually integrated into the processor itself, and an optional I/O APIC on a system bus. The first APIC was the 82489DX{{snd}} it was a discrete chip that functioned both as local and I/O APIC. The 82489DX enabled construction of [[symmetric multiprocessor]] (SMP) systems with the [[Intel 486]] and early [[Pentium]] processors; for example, the reference two-way 486 SMP system used three 82489DX chips, two as local APICs and one as I/O APIC. Starting with the [[P54C]] processor, the local APIC functionality was integrated into the Intel processors' silicon. The first dedicated I/O APIC was the Intel 82093AA, which was intended for [[PIIX3]]-based systems.

== Overview ==

There are two components in the Intel APIC system, the ''local APIC'' (LAPIC) and the ''I/O APIC''. There is one LAPIC in each CPU in the system. In the very first implementation ('''82489DX'''), the LAPIC was a discrete circuit, as opposed to its thereafterlater implementation in Intel processors' silicon. There is typically one I/O APIC for each peripheral bus in the system. In original system designs, LAPICs and I/O APICs were connected by a dedicated APIC bus. Newer systems use the system bus for communication between all APIC components.

Each APIC, whether a discrete chip or integrated in a CPU, has a version register containing a four-bit version number for its specific APIC implementation. For example, the 82489DX has an APIC version number of 0, while version 1 was assigned to the first generation of local APICs integrated in the Pentium 90 and 100 processors.<ref>[http://www.intel.com/design/archives/processors/pro/docs/242016.htm Intel MultiProcessor Specification], version 1.4, page 3-5, May 1997</ref>

In systems containing an [[Intel 8259|8259]] PIC]], the 8259 may be connected to the LAPIC in the system's bootstrap processor (BSP), or to one of the system's I/O APICs, or both. Logically, however, the 8259 is only connected once at any given time.

==Discrete APIC==

The first-generation Intel APIC chip, the 82489DX, which was meant to be used with [[Intel 80486]] and early Pentium processors, is actually an external local and I/O APIC in one circuit. The Intel MP 1.4 specification refers to it as "discrete APIC" in contrast with the "integrated APIC" found in most of the Pentium processors.<ref>[http://www.intel.com/design/archives/processors/pro/docs/242016.htm Intel MultiProcessor Specification], version 1.4, page 1-4, May 1997</ref> The 82489DX had 16 interrupt lines;<ref name="Ram2001">{{cite book|author=Badri Ram|title=Adv Microprocessors Interfacing|url=https://books.google.com/books?id=eVcEWDIeTYcC&pg=PT314|year=2001|publisher=Tata McGraw-Hill Education|isbn=978-0-07-043448-6|page=314}}</ref> it also had a quirk that it could lose some ISA interrupts.<Refref >{{cite web | website=freebsd.org|title=A Description of the APIC I/O Subsystem | url=http://people.freebsd.org/~fsmp/SMP/papers/apicsubsystem.txt | access-date=14 May 2023}}</ref>

In a multiprocessor 486 system, each CPU had to be paired with its own 82489DX; additionally a supplementary 82489DX had to be used as I/O APIC. The 82489DX could not emulate the 8259A (XT-PIC) so these also had to be included as physical chips for backwards compatibility.<ref>Intel MultiProcessor Specification, version 1.4, page 5-3, May 1997</ref> The 82489DX was a packaged as a 132-pin [[PQFP]].<ref name="Ram2001"/> It was available for USD $26 per 1,000-unit in quantities.<ref>Intel Corporation, "New Product Focus: OEM: Interrupt Controller Optimized for Advanced Operating Systems", Microcomputer Solutions, January/February 1993, page 21</ref>

==Integrated local APICs==

Local APICs (LAPICs) manage all external interrupts for some specific processor in an SMP system. In addition, they are able to accept and generate [[inter-processor interrupt]]s (IPIs) between LAPICs. LAPICsA single LAPIC may support up to 224 usable [[interrupt]] vectors from an I/O APIC. Vector numbers 0 to 31, out of 0 to 255, are reserved for exception handling by x86 processors.

All Intel processors starting with the P5 microarchitecture ([[P54C]]) have a built-in local APIC.<ref name="Mueller2011">{{cite book|author=Scott M. Mueller|title=Upgrading and Repairing PCs|year=2011|publisher=Que Publishing|isbn=978-0-13-268218-3|page=242|edition=20th}}</ref><ref name="timer" /> However, if the local APIC is disabled in a P5 processor, it cannot be re-enabled by software; this limitation no longer exists in the [[P6 (microarchitecture)|P6 processors]] and later ones.<ref name="timer" />

With the introduction of [[Pentium 4 HT]] and [[Pentium D]], each CPU core and each CPU thread have the integrated LAPIC.

The [[Message Signaled Interrupts]] (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.<ref name="up">{{cite web|url=http://msdn.microsoft.com/en-us/windows/hardware/gg462964.aspx|title=Windows Hardware Dev Center|website=msdn.microsoft.com}}</ref> Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.<ref name="msi"/>

The [[Message Signaled Interrupts]] (MSI) feature of the PCI 2.2 and later specifications cannot be used without the local APIC being enabled.<ref name="up">{{cite web|url=http://msdn.microsoft.com/en-us/windows/hardware/gg462964.aspx|title=Windows Hardware Dev Center|website=msdn.microsoft.com|date=June 2017 }}</ref> Use of MSI obviates the need for an I/O APIC. Additionally, up to 224 interrupts are supported in MSI mode, and IRQ sharing is not allowed.<ref name="msi"/>

=== APIC timer ===

Another advantage of the local APIC is that it also provides a high-resolution (on the order of one [[microsecond]] or better) timer that can be used in both interval and one-off mode.<ref name="timer">Uwe Walter, Vincent Oberle [http://telematics.tm.kit.edu/publications/Files/61/walter_ibm_linux_challenge.pdf μ-second precision timer support for the Linux kernel]</ref>

The APIC timer had its initial acceptance woes. A Microsoft document from 2002 (which advocated for the adoption of [[High Precision Event Timer]] instead) criticized the LAPIC timer for having "poor resolution" and stating that "the clocks silicon is sometimes very buggy".<Refref>[{{Cite web |date=2002-09-20 |title=Guidelines For Providing Multimedia Timer Support |url=http://msdn.microsoft.com/en-us/library/windows/hardware/gg463347.aspx Guidelines|archive-url=https://web.archive.org/web/20120728124718/http://msdn.microsoft.com/en-us/library/windows/hardware/gg463347.aspx For|archive-date=2012-07-28 Providing Multimedia Timer Support],|url-status=deviated September 20, 2002|website=Microsoft}}</ref> Nevertheless, the APIC timer is used for example by [[Windows 7]] when [[Profiling (computer programming)|profiling]] is enabled, and by [[Windows 8]] in all circumstances. (Before Windows 8 claimed exclusive rights to this timer, it was also used by some programs like [[CPU-Z]].) Under Microsoft Windows the APIC timer is not a shareable resource.<ref>[http{{Cite web|url=https://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk Windows 8 and APIC timer] {{webarchive |archive-url=https://web.archive.org/web/20140222070735/http://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk|url-status=dead|title=Windows 8 and APIC timer|archive-date=February 22, February 2014|website=social.msdn.microsoft.com|access-date=14 May 2023}}</ref>

The aperiodic interrupts offered by the APIC timer are used by the [[Linux kernel]] [[tickless kernel]]

feature. This optional but default feature is new with 2.6.18. With itWhen enabled on a computer with an APIC timer, the kernel does not use the [[8253]] [[Programmableprogrammable Intervalinterval Timertimer]] for timekeeping.<ref>{{cite web|url=http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802|title=VMware Knowledge Base|website=kb.vmware.com|access-date=2014-02-13|archive-date=2017-02-27|archive-url=https://web.archive.org/web/20170227025032/http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802|url-status=dead}}</ref> A [[VMware]] document notes that "software does not have a reliable way to determine its frequency. Generally, the only way to determine the local APIC timer’s frequency is to measure it using the PIT or CMOS timer, which yields only an approximate result."<ref name="vmware">[http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf Timekeeping in VMware Virtual Machines (for VMware vSphere 5.0, Workstation 8.0, Fusion 4.0)] {{Webarchive|url=https://web.archive.org/web/20160626142735/http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf |date=2016-06-26 }}, page 8</ref>

==I/O APICs==

I/O APICs contain a redirection table, which is used to route the interrupts it receives from peripheral buses to one or more local APICs. Early I/O APICs (like 82489DX, SIO.A and PCEB/ESC) only had support for 16 interrupt lines, but later ones like 82093AA (separate chip for PIIX3/PIIX4) had support for 24 interrupt lines.<ref name="msi">James Coleman, [http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf Reducing Interrupt Latency Through the Use of Message Signaled Interrupts], pp. 10-11</ref> It was packaged as a 64-Pin [[PQFP]].<ref name="i82093AA">{{cite web|url=http://www.intel.com/design/chipsets/datashts/290566.htm|title=Resource & Design Center for Development with Intel|website=Intel}}</ref> The 82093AA normally connected to the [[PIIX3]]/[[PIIX4]] and used its integrated legacy 8259 PICs.<ref name="i82093AA"/> The [[I/O Controller Hub#ICH|ICH1]] reintegratedintegrated anthe I/O APIC,. likeAn theintegrated PIIXI/O predecessorAPIC SIO.Aof (formodern ISA)chipsets andmay PCEB/ESCprovide (formore EISA)than 24 interrupt lines.<ref>{{cite web |url=https://cdrdv2-public.intel.com/620855/620855-002.pdf |title=Intel 400 Series Chipset Family Platform Controller Hub Datasheet - Volume 2 of 2 |date=May 2020 |publisher=[[Intel]]}}</ref>

According to a 2009 Intel benchmark using [[Linux]], the I/O APIC reduced interrupt latency by a factor of almost three relative to the 8259 emulation (XT-PIC), while using MSI reduced the latency even more, by a factor of nearly seven relative to the XT-PIC baseline.<ref>James Coleman, [http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/msg-signaled-interrupts-paper.pdf Reducing Interrupt Latency Through the Use of Message Signaled Interrupts], p. 19</ref>

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The improved interface reduces the number of needed APIC register accesses for sending [[inter-processor interrupt]]s (IPIs). Because of this advantage, [[Kernel-based Virtual Machine|KVM]] can and does emulate the x2APIC for older processors that do not physically support it, and this support is exposed from [[QEMU]] going back to [[Conroe (microprocessor)|Conroe]] and even for AMD [[Opteron]] G-series processors (neither of which natively support x2APIC).<ref>{{cite web|url=https://lists.gnu.org/archive/html/qemu-devel/2013-07/msg03756.html|title=Re: [Qemu-devel] [Question] why x2apic's set by default without host sup|website=lists.gnu.org}}</ref><ref>{{cite web|url=http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg02441.html|title=[Qemu-devel] [PATCH] target-i386: enable x2apic by default on more recen|website=lists.nongnu.org}}</ref>

[[APICv]] is the Intel's brand name for [[hardware virtualization]] support aimed at reducing interrupt overhead in guests. APICv was introduced in the [[Ivy Bridge-EP]] processor series, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).<ref>{{cite web |author=Jun Nakajima |title=Reviewing Unused and New Features for Interrupt/APIC Virtualization |url=http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-intel-vt-feat-nakajima.pdf |website=Linux |access-date=14 May 2023 |year=2012}}</ref><ref>{{cite web|url=https://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone|title=APIC Virtualization Performance Testing and Iozone* - Intel® Software|website=software.intel.com}}</ref><ref>http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-e5-4600-v2-brief.pdf</ref> AMD announced a similar technology called [[Advanced Virtual Interrupt Controller|AVIC]],<ref>Wei Huang, [http://www.slideshare.net/xen_com_mgr/introduction-of-amd-virtual-interrupt-controller Introduction of AMD Advanced Virtual Interrupt Controller], XenSummit 2012</ref><ref>{{cite web |author=Jörg Rödel |title=Next-generation Interrupt Virtualization for KVM |url=http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-interrupt-virt-kvm-roedel.pdf |website=Linux |access-date=14 May 2023 |date=August 2012}}</ref> it is available family [[Excavator (microarchitecture)|15h models 6Xh (Carrizo) processors]] and newer.<ref>{{cite web|url=https://www.mail-archive.com/[e-mail]/msg81719.html|title=[Xen-devel] [RFC PATCH 0/9] Introduce AMD SVM AVIC|website=www.mail-archive.com}}</ref>

== Issues ==

{{unreferenced| section|date=February 2014}}

There are a number of known bugs in implementations of APIC systems, especially with concern to how the [[Intel 8254|8254]] is connected. Defective [[BIOS]]es may not set up interrupt routing properly, or provide incorrect [[Advanced Configuration and Power Interface|ACPI]] tables and Intel [[MultiProcessor Specification]] (MPS) tables.

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== Competition ==

{{further|OpenPIC and IBM MPIC}}

[[AMD]] and [[Cyrix]] once proposed a somewhat similar-in-purpose [[OpenPIC]] architecture supporting up to 32 processors;<ref>{{cite web |url=https://www.pcmag.com/encyclopedia_term/0,2542,t=OpenPIC&i=48497,00.asp |title=OpenPIC Definition from PC Magazine Encyclopedia |publisher=Pcmag.com |date=1994-12-01 |access-date=2011-11-03 }}{{Dead link|date=August 2025 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> it had at least declarative support from [[IBM]] and [[Compaq]] around 1995.<ref name="Inc.1995">{{cite journal|title=AMD, Cyrix offer up alternative SMP spec|author=Brooke Crothers|journal=[[InfoWorld]]|url=https://books.google.com/books?id=lToEAAAAMBAJ&pg=PA8|date=20 March 1995|page=8|issn=0199-6649}}</ref> No x86 motherboard was released with OpenPIC however.<ref>André D. Balsa, [http://linuxgazette.net/issue24/Article3e-7.html Note attached to "Linux Benchmarking: Part III -- Interpreting Benchmark Results"] appearing in Issue 24 of Linux Gazette, January 1998</ref> After the OpenPIC's failure in the x86 market, AMD licensed Intel's APIC for its [[AMD Athlon]] and later processors.

IBM however developed their [[OpenPIC and MPIC|MultiProcessor Interrupt Controller]] (MPIC) based on the OpenPIC register specifications.<ref>IBM [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/$file/mpic_db_05_16_2011.pdf Multiprocessor Interrupt Controller. Data Book] {{webarchive|url=https://web.archive.org/web/20140223012746/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F27971551C9EED8E8525774A0048770A/%24file/mpic_db_05_16_2011.pdf |date=2014-02-23 }}</ref> MPIC was used in [[PowerPC]] based designs, including those of IBM, for instance in some [[RS/6000]] systems,<ref>Arca Systems TTAP Evaluation Facility [http://www.ashtonlabs.com/library/FERs/CSC-FER-98-004.pdf The IBM Corporation RS/6000 Distributed System Running AIX Version 4.3.1. TCSEC Evaluated C2 Security], p. 29</ref> but also by Apple, as late as their [[Power Mac G5]]s.<ref>{{cite book|url=http://www.informit.com/articles/article.aspx?p=606582|title=Take a Look Inside the G5-Based Dual-Processor Power Mac|first=Amit|last=Singh|date=13 October 2006|via=informIT database}}</ref><ref>[https://developer.apple.com/legacy/library/documentation/Hardware/Developer_Notes/Macintosh_CPUs-G5/PowerMacG5/PowerMacG5.pdf Power Mac G5 Developer Note (Legacy)], p. 26</ref>

== See also ==

* [[Intel 8259]]

* [[Programmable interrupt controller]] (PIC)

* [[Inter-processor interrupt]] (IPI)

* [[Interrupt]]

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== External links ==

* [http://www.intel.com/content/dam/doc/specification-update/64-architecture-x2apic-specification.pdf Intel 64 Architecture x2APIC Specification] (PDF)

* More information on the Intel x2APIC Architecture can be found in the ''Intel 64 and IA-32 [http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html Architectures Software Developer's Manuals]''

{{Intel}}

[[Category:Motherboard]]

[[Category:Interrupts]]