Multiple instruction, multiple data: Difference between revisions

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{{Short description|Computing technique employed to achieve parallelism}}

<noinclude>{{User:RMCD bot/subject notice|1=multiple instruction, multiple data|2=Talk:MIMD#Requested move 21 January 2022}}

</noinclude>{{Flynn's Taxonomy}}

[[Image:MIMD.svg|right|225px]]

In [[computing]], '''multiple instruction, multiple data''' ('''MIMD''') is a technique employed to achieve parallelism. Machines using MIMD have a number of [[processorsprocessor core]]s that function [[asynchrony (computing)|asynchronously]] and independently. At any time, different processors may be executing different instructions on different pieces of data.

MIMD architectures may be used in a number of application areas such as [[computer-aided design]]/[[computer-aided manufacturing]], [[Computer simulation|simulation]], [[Scientific modelling|modeling]], and as [[communication switches]]. MIMD machines can be of either [[Shared memory (interprocess communication)|shared memory]] or [[distributed memory]] categories. These classifications are based on how MIMD processors access memory. Shared memory machines may be of the [[Bus network|bus-based]], extended, or [[hierarchical#Computation and electronics|hierarchical]] type. Distributed memory machines may have [[Grid network|hypercube]] or [[Mesh networking|mesh]] interconnection schemes.

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An example of MIMD system is [[Xeon Phi|Intel Xeon Phi]], descended from [[Larrabee (microarchitecture)|Larrabee]] microarchitecture.<ref>{{Cite web|url=http://perilsofparallel.blogspot.gr/2008/09/larrabee-vs-nvidia-mimd-vs-simd.html|title = The Perils of Parallel: Larrabee vs. Nvidia, MIMD vs. SIMD|date = 19 September 2008}}</ref> These processors have multiple processing cores (up to 61 as of 2015) that can execute different instructions on different data.

Most parallel computers, as of 2013, are MIMD systems.<ref>{{cite web|url=http://software.intel.com/en-us/articles/mimd |title=ArchivedMIMD copy&#124; Intel® Developer Zone |access-date=2013-10-16 |url-status=dead |archive-url=https://web.archive.org/web/20131016215430/http://software.intel.com/en-us/articles/mimd |archive-date=2013-10-16 }}</ref>

==Shared memory model==

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== Distributed memory ==

In distributed memory MIMD( (multiple instruction, multiple data) machines, each processor has its own individual memory ___location. Each processor has no direct knowledge about other processor's memory. For data to be shared, it must be passed from one processor to another as a message. Since there is no shared memory, contention is not as great a problem with these machines. It is not economically feasible to connect a large number of processors directly to each other. A way to avoid this multitude of direct connections is to connect each processor to just a few others. This type of design can be inefficient because of the added time required to pass a message from one processor to another along the message path. The amount of time required for processors to perform simple message routing can be substantial. Systems were designed to reduce this time loss and [[Connection Machine|hypercube]] and [[Mesh networking|mesh]] are among two of the popular interconnection schemes.

Examples of distributed memory (multiple computers) include [[Massively parallel (computing)|MPP (massively parallel processors)]], [[Computer cluster|COW (clusters of workstations)]] and NUMA ([[non-uniform memory access]]). The former is complex and expensive: Many super-computers coupled by broad-band networks. Examples include hypercube and mesh interconnections. COW is the "home-made" version for a fraction of the price.<ref name=tanenbaum/>

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==See also==

* [[Symmetric multiprocessing|SMP]]

* [[Non-Uniform Memory Access|NUMA]]

* [[Torus interconnect]]

* [[Flynn's taxonomy]]

* [[MapReduce]]

* [[Non-Uniform Memory Access|NUMA]]

* [[Symmetric multiprocessing|SMP]]

* [[SPMD]]

* [[Superscalar]]

* [[Torus interconnect]]

* [[Very long instruction word]]