Princeton Application Repository for Shared-Memory Computers: Difference between revisions

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|archive-date=2013-01-23

|url-status=dead

}}</ref><ref name="mattsonblog">{{Cite web |url=http://blogs.intel.com/research/2008/02/designing_future_computers_wit.php |title=Designing future computers with future workloads |publisher=Research@Intel |access-date=2008-02-26}}{{dead link|archive-date=August2008-09-06 |archive-url=https://web.archive.org/web/20080906112505/http://blogs.intel.com/research/2008/02/designing_future_computers_wit.php |url-status=dead 2022}}</ref> Since its inception the benchmark suite has become a community project that is continued to be improved by a broad range of research institutions.<ref name="gabeweb">{{Cite web |url=http://www.gabeoneda.com/node/39 |title=Intel CTO looks into the future: Measuring the value and need for multi-core |publisher=Gabe on EDA |access-date=2006-08-31}}{{dead link|archive-date=August2008-04-08 |archive-url=https://web.archive.org/web/20080408210713/http://www.gabeoneda.com/node/39 |url-status=dead 2022}}</ref> PARSEC is freely available and is used for both academic and non-academic research.<ref name="parsecweb">{{Cite web |url=http://parsec.cs.princeton.edu/ |title=The PARSEC Benchmark Suite |publisher=Princeton University |access-date=2008-01-05}}</ref><ref name="bhadauria09parsec">{{Citation |title=Proceedings of the 2009 IEEE International Symposium on Workload Characterization |date=October 2009 |last1=Bhadauria |last2=Weaver |last3=McKee |first1=Major |first2=Vincent M. |first3=Sally A. |contribution=Understanding PARSEC Performance on Contemporary CMPs |contribution-url=http://www.iiswc.org/iiswc2009/ |publisher=IEEE}}</ref><ref name="barrowwilliams09parsec">{{Citation |title=Proceedings of the 2009 IEEE International Symposium on Workload Characterization |date=October 2009 |last1=Barrow-Williams |last2=Fensch |last3=Moore |first1=Nick |first2=Christian |first3=Simon |contribution=A Communication Characterization of SPLASH-2 and PARSEC |contribution-url=http://www.iiswc.org/iiswc2009/ |publisher=IEEE}}</ref>

== Background ==

The introduction of chip-multiprocessors required computer manufacturers to rewrite software for the first time to take advantage of parallel processing capabilities, including rewriting existing systems for testing and development.<ref name="mattsonblog"/><ref name="rabaey08future">{{Citation

|last1=Rabaey
|first1=Jan M.

|last2=Burke
|first2=Daniel

|last3=Lutz
|first3=Ken

|last4=Wawrzynek
|first4=John

|contribution=Workloads of the Future

|contribution-url=http://www2.computer.org/cms/Computer.org/ComputingNow/homepage/0908/WorkloadsoftheFuture.pdf

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|publisher=IEEE

|date=July–August 2008

|access-date=2010-02-12

}}{{dead link|date=August 2022}}</ref> At that time parallel software only existed in very specialized areas. However, before chip-multiprocessors became commonly available software developers were not willing to [[Parallelization|rewrite]] any mainstream programs, which means hardware manufacturers did not have access to any programs for test and development purposes that represented the expected real-world program behavior accurately. This posed a hen-and-egg problem that motivated a new type of benchmark suite with parallel programs that could take full advantage of chip-multiprocessors.

|archive-date=2011-08-07

|archive-url=https://web.archive.org/web/20110807224952/http://www2.computer.org/cms/Computer.org/ComputingNow/homepage/0908/WorkloadsoftheFuture.pdf

|url-status=dead

}}{{dead link|date=August 2022}}</ref> At that time parallel software only existed in very specialized areas. However, before chip-multiprocessors became commonly available software developers were not willing to [[Parallelization|rewrite]] any mainstream programs, which means hardware manufacturers did not have access to any programs for test and development purposes that represented the expected real-world program behavior accurately. This posed a hen-and-egg problem that motivated a new type of benchmark suite with parallel programs that could take full advantage of chip-multiprocessors.

PARSEC was created to break this circular dependency. It was designed to fulfill the following five objectives:<ref name="bienia08parsec">{{Citation

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# The suite supports research

Traditional benchmarks that were publicly available before PARSEC were generally limited in their scope of included application domains or typically only available in an unparallelized, serial version. Parallel programs were only prevalent in the ___domain of [[High-Performance Computing]] and on a much smaller scale in business environments.<ref name=parsec_splash_comparison>{{Cite book | last1 = Bienia | first1 = C. | last2 = Kumar | first2 = S. | last3 = Kai Li | doi = 10.1109/IISWC.2008.4636090 | chapter = PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors | title = 2008 IEEE International Symposium on Workload Characterization | pages = 47 | year = 2008 | isbn = 978-1-4244-2777-2 | s2cid = 1805881 }}</ref> [[multi-core processor|Chip-multiprocessors]] however were expected to be heavily used in all areas of computing such as with parallelized consumer applications.

== Workloads ==