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{{Short description|Electronic device}}
[[File:SET schematic2.jpg|thumb|Schematic of a basic SET and its internal electrical components]]
A '''single-electron transistor''' ('''SET''') is a sensitive electronic device based on the [[Coulomb blockade]] effect. In this device the electrons flow through a [[tunnel junction]] between source/drain to a [[quantum dot]] (conductive island). Moreover, the electrical potential of the island can be tuned by a third electrode, known as the gate, which is capacitively coupled to the island. The conductive island is sandwiched between two tunnel junctions<ref>{{cite journal|last1=Mahapatra|first1=S.|last2=Vaish|first2=V.|last3=Wasshuber|first3=C.|last4=Banerjee|first4=K.|last5=Ionescu|first5=A.M.|title=Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design|journal=IEEE Transactions on Electron Devices|volume=51|issue=11|year=2004|pages=1772–1782|issn=0018-9383|doi=10.1109/TED.2004.837369|bibcode=2004ITED...51.1772M|s2cid=15373278}}</ref> modeled by capacitors, <math>C_{\rm D}</math> and <math>C_{\rm S}</math>, and resistors, <math>R_{\rm D}</math> and <math>R_{\rm S}</math>, in parallel.
== History ==
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[[File:Single electron transistor.svg|thumb|right|Left to right: energy levels of source, island and drain in a single-electron transistor for the blocking state (upper part) and transmitting state (lower part).]]
The SET has, like the [[field-effect transistor|FET]], three electrodes: source, drain, and a gate. The main technological difference between the transistor types is in the channel concept. While the channel changes from insulated to conductive with applied gate voltage in the FET, the SET is always insulated. The source and drain are coupled through two
The current, <math>I,</math> from source to drain follows [[Ohm's law]] when <math>V_{\rm SD}</math> is applied, and it equals <math>\tfrac{V_{\rm SD}}{R},</math> where the main contribution of the resistance, <math>R,</math> comes from the tunnelling effects when electrons move from source to QD, and from QD to drain. <math>V_{\rm G}</math> regulates the resistance of the QD, which regulates the current. This is the exact same behaviour as in regular FETs. However, when moving away from the macroscopic scale, the quantum effects will affect the current, <math>I.</math>
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The background charge of the dielectric surrounding the QD is indicated by <math>q_0</math>. <math>n_{\rm S}</math> and <math>n_{\rm D}</math> denote the number of electrons tunnelling through the two tunnel junctions and the total number of electrons is <math>n</math>. The corresponding charges at the tunnel junctions can be written as:
:<math>q_{\rm S} = C_{\rm S} V_{\rm S}</math>
:<math>q_{\rm D} = C_{\rm D} V_{\rm D}</math>
:<math>q = q_{\rm D} - q_{\rm S} + q_0 = -ne + q_0,</math>
where <math>C_{\rm S}</math> and <math>C_{\rm D}</math> are the parasitic leakage capacities of the tunnel junctions. Given the bias voltage, <math>V_{\rm bias} = V_{\rm S} + V_{\rm D},</math> you can solve the voltages at the tunnel junctions:
:<math>V_{\rm S} = \frac{C_{\rm D} V_{\rm bias} + ne - q_0}{C_{\rm S} + C_{\rm D}},</math>
:<math>V_{\rm D} = \frac{C_{\rm S} V_{\rm bias} - ne + q_0}{C_{\rm S} + C_{\rm D}}.</math>
The electrostatic energy of a double-connected tunnel junction (like the one in the schematical picture) will be
:<math>E_C = \frac{q_{\rm S}^2}{2 C_{\rm S}} + \frac{q_{\rm D}^2}{2 C_{\rm D}} = \frac{C_{\rm S} C_{\rm D} V_{\rm bias}^2 + (ne - q_0)^2}{2(C_{\rm S} + C_{\rm D})}.</math>
The work performed during electron tunnelling through the first and second transitions will be:
:<math>W_{\rm S} = \frac{n_{\rm S} e V_{\rm bias} C_{\rm D}}{C_{\rm S} + C_{\rm D}},</math>
:<math>W_{\rm D} = \frac{n_{\rm D} e V_{\rm bias} C_{\rm S}}{C_{\rm S} + C_{\rm D}}.</math>
Given the standard definition of free energy in the form:
:<math>F = E_{\rm tot} - W,</math>
where <math>E_{\rm tot} = E_C = \Delta E_F + E_N,</math> we find the free energy of a SET as:
:<math>F(n, n_{\rm S}, n_{\rm D}) = E_C - W = \frac{1}{C_{\rm S} + C_{\rm D}} \left( \frac{1}{2} C_{\rm S} C_{\rm D} V_{\rm bias}^2 + (ne - q_0)^2 + e V_{\rm bias} C_{\rm S} n_{\rm D} + C_{\rm D} n_{\rm S} \right).</math>
For further consideration, it is necessary to know the change in free energy at zero temperatures at both tunnel junctions:
:<math>\Delta F_{\rm S}^{\pm} = F(n \pm 1, n_{\rm S} \pm 1, n_{\rm D}) - F(n, n_{\rm S}, n_{\rm D}) = \frac{e}{C_{\rm S} + C_{\rm D}} \left( \frac{e}{2} \pm (V_{\rm bias} C_{\rm D} + ne - q_0) \right),</math>
:<math>\Delta F_{\rm D}^{\pm} = F(n \pm 1, n_{\rm S}, n_{\rm D} \pm 1) - F(n, n_{\rm S}, n_{\rm D}) = \frac{e}{C_{\rm S} + C_{\rm D}} \left( \frac{e}{2} \pm (V_{\rm bias} C_{\rm S} + ne - q_0) \right),</math>
The probability of a tunnel transition will be high when the change in free energy is negative. The main term in the expressions above determines a positive value of <math>\Delta F</math> as long as the applied voltage <math>V_{\rm bias}</math> will not exceed the threshold value, which depends on the smallest capacity in the system. In general, for an uncharged QD (<math>n = 0</math> and <math>q_0 = 0</math>) for symmetric transitions (<math>C_{\rm S} = C_{\rm D} = C</math>) we have the condition
:<math>V_{\rm th} = \left|V_{\rm bias}\right| \ge \frac{e}{2 C},</math>
(that is, the threshold voltage is reduced by half compared with a single transition).
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In the case where the permeability of the tunnel barriers is very different <math>(R_{T1} \gg R_{T2} = R_T),</math> a stepwise I-V characteristic of the SET arises. An electron tunnels to the island through the first transition and is retained on it, due to the high tunnel resistance of the second transition. After a certain period of time, the electron tunnels through the second transition, however, this process causes a second electron to tunnel to the island through the first transition. Therefore, most of the time the island is charged in excess of one charge. For the case with the inverse dependence of permeability <math>(R_{T1} \ll R_{T2} = R_T),</math> the island will be unpopulated and its charge will decrease stepwise.{{citation needed|date=January 2020}} Only now can we understand the principle of operation of a SET. Its equivalent circuit can be represented as two tunnel junctions connected in series via the QD, perpendicular to the tunnel junctions is another control electrode (gate) connected. The gate electrode is connected to the island through a control tank <math>C_{\rm G}.</math> The gate electrode can change the background charge in the dielectric, since the gate additionally polarizes the island so that the island charge becomes equal to
:<math>q = -ne + q_0 + C_{\rm G}(V_{\rm G} - V_{2}).</math>
Substituting this value into the formulas found above, we find new values for the voltages at the transitions:
:<math>V_{\rm S} = \frac{(C_{\rm D} + C_{\rm G}) V_{\rm bias} - C_{\rm G} V_{\rm G} + ne - q_0}{C_{\rm S} + C_{\rm D}},</math>
:<math>V_{\rm D} = \frac{C_{\rm S} V_{\rm bias} + C_{\rm G} V_{\rm G} - ne + q_0}{C_{\rm S} + C_{\rm D}},</math>
The electrostatic energy should include the energy stored on the gate capacitor, and the work performed by the voltage on the gate should be taken into account in the free energy:
:<math>\Delta F_{\rm S}^{\pm} = \frac{e}{C_{\rm S} + C_{\rm D}} \left( \frac{e}{2} \pm V_{\rm bias}(C_{\rm D} + C_{\rm G}) - V_{\rm G} C_{\rm G} + ne + q_0 \right),</math>
:<math>\Delta F_{\rm D}^{\pm} = \frac{e}{C_{\rm S} + C_{\rm D}} \left( \frac{e}{2} \pm V_{\rm bias} C_{\rm S} + V_{\rm G} C_{\rm G} - ne + q_0 \right).</math>
At zero temperatures, only transitions with negative free energy are allowed: <math>\Delta F_{\rm S} < 0</math> or <math>\Delta F_{\rm D} < 0</math>. These conditions can be used to find areas of stability in the plane <math>V_{\rm bias} - V_{\rm G}.</math>
With increasing voltage at the gate electrode, when the supply voltage is
=== Temperature dependence ===
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The level of the electrical current of the SET can be amplified enough to work with available [[CMOS]] technology by generating a hybrid SET–[[field-effect transistor|FET]] device.<ref name="IonescuMahapatra2004">{{cite journal|last1=Ionescu|first1=A.M.|last2=Mahapatra|first2=S.|last3=Pott|first3=V.|title=Hybrid SETMOS Architecture With Coulomb Blockade Oscillations and High Current Drive|journal=IEEE Electron Device Letters|volume=25|issue=6|year=2004|pages=411–413|issn=0741-3106|doi=10.1109/LED.2004.828558|bibcode=2004IEDL...25..411I|s2cid=42715316}}</ref><ref name="AmatBausells2017">{{cite journal|last1=Amat|first1=Esteve|last2=Bausells|first2=Joan|last3=Perez-Murano|first3=Francesc|title=Exploring the Influence of Variability on Single-Electron Transistors Into SET-Based Circuits|journal=IEEE Transactions on Electron Devices|volume=64|issue=12|year=2017|pages=5172–5180|issn=0018-9383|doi=10.1109/TED.2017.2765003|bibcode=2017ITED...64.5172A|s2cid=22082690}}</ref>
The EU funded, in 2016, project IONS4SET (#688072)<ref>{{cite web|url=http://www.ions4set.eu|title=IONS4SET Website|access-date=2019-09-17}}</ref> looks for the manufacturability of SET–FET circuits operative at room temperature. The main goal of this project is to design a SET-manufacturability process-flow for large-scale operations seeking to extend the use of the hybrid SET–CMOS architectures. To assure room temperature operation, single dots of diameters below 5 nm have to be fabricated and located between source and drain with tunnel distances of a few nanometers.<ref name="KlupfelBurenkov2016">{{cite book|last1=Klupfel|first1=F. J.|title=2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)|last2=Burenkov|first2=A.|last3=Lorenz|first3=J.|chapter=Simulation of silicon-dot-based single-electron memory devices|year=2016|pages=237–240|doi=10.1109/SISPAD.2016.7605191|isbn=978-1-5090-0818-6|s2cid=15721282}}</ref> Up to now there is no reliable process-flow to manufacture a hybrid SET–FET circuit operative at room temperature. In this context, this EU project explores a more feasible way to manufacture the SET–FET circuit by using pillar dimensions of approximately 10 nm.<ref name="Xu2019">{{cite
== See also ==
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