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==Flynn's taxonomy==
{{Main|Flynn's taxonomy}}
Typically, latency oriented processor architectures execute a single task operating on a single data stream, and so they are [[Single instruction, single data|SISD]] under Flynn's taxonomy. Latency oriented processor architectures might also include [[Single instruction, multiple data|SIMD]] instruction set extensions such as Intel [[MMX (instruction set)|MMX]] and [[Streaming SIMD Extensions|SSE]]; even though these extensions operate on large data sets, their primary goal is to reduce overall latency.<ref name=YanSohilin2016/>
==Implementation techniques==
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===Instruction set architecture (ISA)===
{{Main|Instruction set}}
Most architectures today use shorter and simpler instructions, like the [[load/store architecture]], which help in optimizing the instruction pipeline for faster execution. Instructions are usually all of the same size which also helps in optimizing the instruction fetch logic. Such an ISA is called a [[Reduced instruction set computing|RISC]] architecture.<ref>{{cite conference|last1=Bhandarkar|first1=Dileep|last2=Clark|first2=Douglas W. |title=
===Instruction pipelining===
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