Signoff (electronic design automation): Difference between revisions

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{{Short description|Verification stages of electronic designs that must pass before manufacture}}

{{Use American English|date = April 2019}}

In the [[electronic design automation|automated]] design of [[integrated circuit]]s, '''signoff''' (also written as '''sign-off''') checks is the collective name given to a series of verification steps that the design must pass before it can be [[Tape-out|taped out]]. This implies an iterative process involving incremental fixes across the board using one or more check types, and then retesting the design. There are two types of sign-off's: [[front-end sign-off]] and [[back-end sign-off]]. After back-end sign-off, the chip goes to fabrication. After listing out all the features in the specification, the verification engineer will write coverage for those features to identify bugs, and send back the RTL design to the designer. Bugs, or defects, can include issues like missing features (comparing the layout to the specification), errors in design (typo and functional errors), etc. When the coverage reaches a maximum% percentage then the verification team will sign it off. By using a methodology like UVM, OVM, or VMM, the verification team develops a reusable environment. Nowadays, UVM is more popular than others.

== History ==

DurinDuring the late 1960s Duringengineers at semiconductor companies like Intel used [[rubylith]] for the semiconductorproduction photomasksof andsemiconductor layoutlithography designphotomasks. Manually drawn [[Circuit diagram|circuit draft schematics]] of the semiconductor devices made by engineers were transeferred manually onto a [[Paper size|D-sized]] paper[[vellum]] sheets by a skilled schematic designer to make a physical layout of the device on a photomask.<ref name=":0">{{Cite journal |date=2001 |title=Recollections of Early Chip Development at Intel |url=https://deramp.com/downloads/mfe_archive/050-Component%20Specifications/Intel/Recollections%20of%20Early%20Chip%20Dev.pdf |journal=Intel technologyTechnology journalJournal |volume=5 |issue=2001 |issn=1535-864X}}</ref>{{r|:0|pp=6}}

The lattervellum would be later hand-checked and ''signed off'' by the original engineer; all edits to the schematics would also be noted, checked, and, again, ''signed off''.{{r|:0|pp=6}}

== Check types ==

Signoff checks have become more complex as [[VLSI]] designs approach [[22nm]] and below process nodes, because of the increased impact of previously ignored (or more crudely approximated) second-order effects. There are several categories of signoff checks.

* [[Layout Versus Schematic]] (LVS) – Also known as schematic verification, this is used to verify that the [[placement (electronic design automation)|placement]] and [[routing (electronic design automation)|routing]] of the [[standard cell]]s in the design has not altered the functionality of the constructed circuit.

* [[Design rule checking]] (DRC) – Also sometimes known as geometric verification, this involves verifying if the design can be reliably [[semiconductor fabrication|manufactured]] given current photolithography limitations. In advanced process nodes, [[Design for manufacturability (IC)|DFM]] rules are upgraded from optional (for better yield) to required.

*[[Layout Versus Schematic]] (LVS) – Also known as schematic verification, this is used to verify that the [[placement (electronic design automation)|placement]] and [[routing (electronic design automation)|routing]] of the [[standard cell]]s in the design has not altered the functionality of the constructed circuit.

* [[Formal verification]] – Here, the logical functionality of the post-[[Integrated circuit layout|layout]] netlist (including any layout-driven optimization) is verified against the pre-layout, post-[[logic synthesis|synthesis]] [[netlist]].

* [[Power network design (IC)|Voltage drop]] analysis – Also known as IR-drop analysis, this check verifies if the [[Power network design (IC)|power grid]] is strong enough to ensure that the [[IC power supply pin|voltage]] representing the binary '''high''' value never dips lower than a set margin (below which the circuit will not function correctly or reliably) due to the combined switching of millions of transistors.