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{{Short description|Type of integrated circuit}}

[[File:ZX81 ULA.jpg|thumb|Sinclair ZX81 ULA]]

A '''gate array''' is an approach to the design and manufacture of [[application-specific integrated circuit]]s (ASICs) using a [[semiconductor device fabrication|prefabricated]] chip with components that are later interconnected into logic devices (e.g. [[NAND gate|NAND gates]]s, [[Flip-flop (electronics)|flip-flops]], etc.) according to a custom order by adding metal interconnect layers in the factory. It was popular during the upheaval in the semiconductor industry in 80sthe 1980s, and its usage declined by the end of 90sthe 1990s.<ref>{{Cite book |last1=Pearson |first1=Ed |last2=Bethel |first2=Cindy L. |chapter=A design review: Concepts for mitigating SQL injection attacks |date=April 2016 |title=2016 4th International Symposium on Digital Forensic and Security (ISDFS) |chapter-url=https://doi.org/10.1109/isdfs.2016.7473537 |publisher=IEEE |pages=169 |doi=10.1109/isdfs.2016.7473537 |isbn=978-1-4673-9865-7 }}</ref>

Similar technologies have also been employed to design and manufacture analog, analog-digital, and structured arrays, but, in general, these are not called gate arrays.

Gate arrays have also been known as '''uncommitted logic arraysarray'''s (''ULAs''), which also offered linear circuit functions,<ref name="ferranti_ula2000">{{ cite book | url=https://archive.org/details/FerrantiULA2000SeriesDatasheet/mode/1up | title=The 224 Cell Uncommitted Array Family | publisher=Ferranti Electronic Components Division | date=March 1977 | access-date=23 February 2021 | pages=1 }}</ref> and ''semi-custom chips''.{{cn|date=June 2022}}

== History ==

=== Development ===

Gate arrays had several concurrent development paths. [[Ferranti]] in the UK pioneered commercializing [[bipolar transistor|bipolar]] ULA technology,<ref name="bteng198307">{{ cite journal | url=https://archive.org/details/bte-198307/page/n19/mode/2up | title=The Use of Gate Arrays in Telecommunications | journal=British Telecommunications Engineering | last1=Grierson | first1=J. R. | date=July 1983 | access-date=26 February 2021 | volume=2 | issue=2 | pages=78–80 | issn=0262-401X | quote=In the UK, Ferranti, with their bipolar collector diffused isolation (CDI) arrays, pioneered the commercial use of gate arrays and for many years this was by far the most widely used technology. }}</ref> offering circuits of "100 to 10,000 gates and above" by 1983.<ref name="btj198301">{{ cite journal | url=https://archive.org/details/btj-198301/page/n71/mode/1up | title=Everybody's talking about Ferranti ICs. | journal=British Telecom Journal | volume=3 | issue=4 | date=January 1983 | access-date=23 January 2021 }}</ref><ref name="ferranti_quickref">{{ cite book | url=https://archive.org/details/FerrantiQ.RefULA1984/page/n1/mode/1up | title=Ferranti Discrete and Integrated Circuits Quick Reference Guide | publisher=Ferranti plc. | date=1982 | access-date=23 February 2021 | pages=IC4 }}</ref> The company's early lead in semi-custom chips, with the initial application of a ULA integrated circuit involving a camera from [[Rollei]] in 1972, expanding to "practically all European camera manufacturers" as users of the technology, led to the company's dominance in this particular market throughout the 1970s. However, by 1982, as many as 30 companies had started to compete with Ferranti, reducing the company's market share to around 30 percent. Ferranti's "major competitors" were other British companies such as Marconi and Plessey, both of which had licensed technology from another British company, Micro Circuit Engineering.<ref name="heidelberg19821006_ics">{{ cite magazine | url=https://archive.org/details/jprs-report_jprs-82727/page/10/mode/2up | title=Great Britain Develops Semicustom and Custom ICs | magazine=Heidelberg Elektronik Industrie | date=6 October 1982 | access-date=4 March 2022 | last1=Turmaine | first1=Bradley | pages=43–46 }}</ref> A contemporary initiative, UK5000, also sought to produce a CMOS gate array with "5,000 usable gates", with involvement from [[British Telecom]] and a number of other major British technology companies.<ref name="bteng198610_silicon">{{ cite journal | url=https://archive.org/details/bte-198610/page/n41/mode/2up | title=Silicon Micro-Electronics at British Telecom Research Laboratories | journal=British Telecommunications Engineering | date=October 1986 | access-date=4 March 2022 | pages=230–236 }}</ref>

[[IBM]] developed proprietary bipolar master slices that it used in mainframe manufacturing in the late 1970s and early 1980s, but never commercialized them externally. [[Fairchild Semiconductor]] also flirted briefly in the late 1960s with bipolar arrays [[diode–transistor logic]] and transistor–transistortransistor-transistor logic called Micromosaic and Polycell.<ref name=":0">{{Cite web|url=http://www.computerhistory.org/siliconengine/application-specific-integrated-circuits-employ-computer-aided-design/|title=1967: Application Specific Integrated Circuits employ Computer-Aided Design|websitework=The Silicon Engine|publisher=[[Computer History Museum]]|access-date=2018-01-28}}</ref>

[[CMOS]] (complementary [[metal–oxide–semiconductor]]) technology opened the door to the broad commercialization of gate arrays. The first CMOS gate arrays were developed by Robert Lipp<ref name=":1">{{Cite book|url=http://www.computerhistory.org/collections/catalog/102706880|title=Lipp, Bob oral history|websitepublisher=[[Computer History Museum]]|date=14 February 2017 |access-date=2018-01-28}}</ref><ref>{{Cite web|url=http://www.computerhistory.org/siliconengine/people/|title=People|websitework=The Silicon Engine|publisher=Computer History Museum|access-date=2018-01-28}}</ref> in 1974 for International Microcircuits, Inc.<ref name=":0" /> (IMI) a Sunnyvale photo-mask shop started by Frank Deverse, Jim Tuttle and Charlie Allen, ex-IBM employees. This first product line employed [[10 µmμm process|7.5 micron]] single-level metal CMOS technology and ranged from 50 to 400 [[metal gate|gates]]. [[Computer-aided design]] (CAD) technology at the time was very rudimentary due to the low processing power available, so the design of these first products was only partially automated.

This product pioneered several features that went on to become standard onin future designs. The most important were: the strict organization of [[NMOS logic|n-channel]] and [[PMOS logic|p-channel transistors]] in 2-3 row pairs across the chip; and running all interconnect on grids rather than minimum custom spacing, which had been the standard until then. This later innovation paved the way to full automation when coupled with the development of 2-layer CMOS arrays. Customizing these first parts was somewhat tedious and error -prone due to the lack of good software tools.<ref name=":0" /> IMI tapped into PC board development techniques to minimize manual customization effort. Chips at the time were designed by hand, drawing all components and interconnectinterconnecting on precision gridded Mylar sheets, using colored pencils to delineate each processing layer. [[Rubylith]] sheets were then cut and peeled to create a (typically) 200x to 400x scale representation of the process layer. This was then photo-reduced to make a 1x mask. Digitization rather than rubylith cutting was just coming in as the latest technology, but initially, it only removed the rubylith stage; drawings were still manual and then "hand" digitized. PC boards, meanwhile, had moved from custom rubylith to PC tape for interconnects. IMI created to-scale photo- enlargements of the base layers. Using decals of logic gate connections and PC tape to interconnect these gates, custom circuits could be quickly laid out by hand for these relatively small circuits, and photo-reduced using existing technologies.

After a falling out with IMI, Robert Lipp went on to start California Devices, Inc. (CDI) in 1978 with two silent partners, Bernie Aronson, and Brian Tighe. CDI quickly developed a product line competitive to IMI and, shortly thereafter, a 5 -micron silicon gate single -layer product line with densities of up to 1,200 gates. A couple of years later, CDI followed up with "channel-less" gate arrays that reduced the row blockages caused by a more complex silicon underlayer that pre-wired the individual transistor connections to locations needed for common logic functions, simplifying the first -level metal interconnect. This increased chip densities by 40%, significantly reducing manufacturing costs.<ref name=":1" />

=== Innovation ===

[[File:Timex Sinclair 1000 Motherboard BL (cropped Ferranti ULA).jpg|thumb|Ferranti {{abbr|ULA|Uncommitted Logic Array}} 2C210E on a [[Timex Sinclair 1000]] motherboard]]

Early gate arrays were low -performance and relatively large and expensive compared to state-of-the-art n-MOS technology then being used for custom chips. CMOS technology was being driven by very low -power applications such as watch chips and battery -operated portable instrumentation, not performance. They were also well under the performance of the existing dominant logic technology, [[transistor–transistor logic families]]. However, there were many niche applications where they were invaluable, particularly in low power, size reduction, portable and aerospace applications as well as time-to-market sensitive products. Even these small arrays could replace a board full of transistor–transistor logic gates if performance were not an issue. A common application was combining a number of smaller circuits that were supporting a larger LSI circuit on a board was affectionately known as "garbage collection". And the low cost of development and custom tooling made the technology available to the most modest budgets. Early gate arrays played a large part in the [[Citizens band radio#1970s popularity|CB craze in the 1970s]] as well as a vehicle for the introduction of other later mass-produced products such as modems and cell phones.

By the early 1980s, gate arrays were starting to move out of their niche applications to the general market. Several factors in technology and markets were converging. Size and performance were increasing; automation was maturing; the technology became "hot" when in 1981 IBM introduced its new flagship [[IBM 308X|3081]] mainframe with CPU comprising gate arrays,;. theyThey were used in a consumer product, the ZX81;, and new entrants to the market increased visibility and credibility.<ref>{{cite book |first=Chris |last=Smith |title=The ZX Spectrum ULA: How To Design A Microcomputer |publisher=ZX Design and Media |oclc=751703922 |date=2010 |isbn=9780956507105 |pages= |url=http://www.zxdesign.info/book/insideULA.shtml}}</ref><ref>{{cite web |title=Uncommitted IC logic |date=5 April 1980 |work=Design How-To |publisher=EDN |url=https://www.edn.com/uncommitted-ic-logic/}}</ref>

In 1981, [[Wilfred Corrigan]], Bill O'Meara, Rob Walker, and Mitchell "Mick" Bohn founded [[LSI Corporation|LSI Logic]].<ref>{{Cite book|url=http://www.computerhistory.org/collections/catalog/102746194|title=LSI Logic oral history panel {{!}} 102746194|websitepublisher=Computer History Museum|date=30 November 2011 |access-date=2018-01-28}}</ref> Their initial intention was to commercialize emitter coupled logic gate arrays, but discovered the market was quickly moving towards CMOS. Instead, they licensed CDI's silicon gate CMOS line as a second source. This product established them in the market while they developed their own proprietary 5 -micron 2-layer metal line. This latter product line was the first commercial gate array product amenable to full automation. LSI developed a suite of proprietary development tools that allowed users to design their own chip from their own facility by remote login to LSI Logic's system.

[[Sinclair Research]] ported an enhanced [[Sinclair ZX80|ZX80]] design to a ULA chip for the [[Sinclair ZX81|ZX81]], and later used a ULA in the [[ZX Spectrum]]. A compatible chip was made in Russia as T34VG1.<ref>[[:ru:Т34ВГ1|Т34ВГ1]] — article about the ZX Spectrum ULA compatible chip {{in lang|ru}}</ref> [[Acorn Computers]] used several ULA chips in the [[BBC Micro]], and later a single ULA for the [[Acorn Electron]]. Many other manufacturers from the time of the [[home computer]] boom period used ULAs in their machines. The [[IBM PC]] took over much of the personal computer market, and the sales volumes made full-custom chips more economical. Commodore's Amiga series used gate arrays for the Gary and Gayle custom- chips, as their code- names may suggest.

In an attempt to reduce the costs and increase the accessibility of gate array design and production, Ferranti introduced in 1982 a computer-aided design tool for their uncommitted logic array (ULA) product called ULA Designer. Although costing £46,500 to acquire, this tool promised to deliver reduced costs of around £5,000 per design plus manufacturing costs of £1-2 per chip in high volumes, in contrast to the £15,000 design costs incurred by engaging Ferranti's services for the design process.<ref name="design198203_ferranti">{{ cite magazine | url=https://archive.org/details/sim_design_1982-03_399/page/n20/mode/1up | title=Make chips at home | magazine=Design | date=March 1982 | access-date=1 March 2022 | pages=17 }}</ref> Based on a PDP-11/23 minicomputer running RSX/11M, together with graphical display, keyboard, "digitalizing board", control desk and optional plotter, the solution aimed to satisfy the design needs of gate arrays from 100 to 10,000 gates, with the design being undertaken entirely by the organisation acquiring the solution, starting with a "logic plan", proceeding through the layout of the logic in the gate array itself, and concluding with the definition of a test specification for verification of the logic and for establishing an automated testing regime. Verification of completed designs was performed by "external specialists" after the transfer of the design to a "CAD center" in Manchester, England or Sunnyvale, California, potentially over the telephone network. Prototyping completed designs took an estimated 3 to 4 weeks. The minicomputer itself was also adaptable to run as a laboratory or office system where appropriate.<ref name="dtic_ada352628">{{ cite magazine | url=https://archive.org/details/DTIC_ADA352658/page/n4/mode/1up | title=Ferranti Introduces CAD System for Gate Arrays | magazine=Wuerzburg Elektronikpraxis | date=February 1982 | access-date=1 March 2022 | issue=105 | pages=54 }}</ref>

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=== Alternatives ===

Indirect competition arose with the development of the [[field-programmable gate array]] (FPGA). [[Xilinx]] was founded in 1984, and its first products were much like early gate arrays, slow and expensive, fit only for some niche markets. However, [[Moore's law|Moore's Law]] quickly made them a force and, by the early 1990s, were seriously disrupting the gate array market.

Designers still wished for a way to create their own complex chips without the expense of full-custom design, and eventually, this wish was granted with the arrival of not only the FPGA, but [[complex programmable logic device]] (CPLD), metal configurable standard cells (MCSC), and structured ASICs. Whereas a gate array required a back -end semiconductor wafer foundry to deposit and etch the interconnections, the FPGA and CPLD had user -programmable interconnections. Today's approach is to make the prototypes by FPGAs, as the risk is low and the functionality can be verified quickly. For smaller devices, production costcosts are sufficiently low. But for large FPGAs, production is very expensive, power -hungry, and in many cases, do not reach the required speed. To address these issues, several ASIC companies like BaySand, Faraday, Gigoptics, and others offer FPGA to ASIC conversion services.

=== Decline ===

While the market boomed, profits for the industry were lacking. Semiconductors underwent a series of rolling [[List of recessions in the United States|recessions]] during the 1980s that created a boom-bust cycle. The 1980 and 1981–1982 general recessions were followed by high -interest rates that curbed capital spending. This reduction played havoc on the semiconductor business, thatwhich at the time was highly dependent on capital spending. Manufacturers desperate to keep their fab plants full and afford constant modernization in a fast -moving industry became hyper-competitive. The many new entrants to the market drove gate array prices down to the marginal costs of the silicon manufacturers. Fabless companies such as LSI Logic and CDI survived on selling design services and computer time rather than on the production revenues.<ref name=":1" />

As of the early 21st century, the gate array market was a remnant of its former self, driven by the FPGA conversions done for cost or performance reasons. IMI moved out of gate arrays into mixed -signal circuits and was later acquired by Cypress Semiconductor in 2001; CDI closed its doors in 1989; and LSI Logic abandoned the market in favor of standard products and was eventually acquired by Broadcom.<ref>{{Cite web|url=http://www.computerhistory.org/siliconengine/companies/|title=Companies|websitework=The Silicon Engine|publisher=Computer History Museum|access-date=2018-01-28}}</ref>

== Design ==

{{Unsourced section|date=April 2023}}

A gate array is a prefabricated silicon chip with most [[transistor]]s having no predetermined function. These transistors can be connected by metal layers to form standard [[Negated AND gate|NAND]] or [[NOR gate|NOR]] [[logic gate]]s. These logic gates can then be further interconnected into a complete circuit on the same or later metal layers. CreationThe creation of a circuit with a specified function is accomplished by adding this final layer or layers of metal interconnects to the chip late in the manufacturing process, allowing the function of the chip to be customized as desired. These layers are analogous to the copper layers of a [[printed circuit board]].

The earliest gate arrays comprised [[bipolar transistors]], usually configured as high -performance [[transistor–transistor logic]], [[emitter-coupled logic]], or [[current-mode logic]] logic configurations. [[CMOS]] (complementary [[metal–oxide–semiconductor]]) gate arrays were later developed and came to dominate the industry.

Gate array master slices with unfinished chips arrayed across a [[wafer (electronics)|wafer]] are usually prefabricated and stockpiled in large quantities regardless of customer orders. The design and fabrication according to the individual customer specifications can be finished in a shorter time than [[standard cell]] or [[full custom]] design. The gate array approach reduces the non -recurring engineering [[Photomask|mask]] costs as fewer custom masks need to be produced. In addition, manufacturing test tooling lead time and costs are reduced — the same test fixtures can be used for all gate array products manufactured on the same [[Die (integrated circuit)|die]] size. Gate arrays were the predecessor of the more complex [[Structured ASIC platform|structured ASIC]]; unlike gate arrays, structured ASICs tend to include predefined or configurable memories and/or analog blocks.

An application circuit must be built on a gate array that has enough gates, wiring, and I/O pins. Since requirements vary, gate arrays usually come in families, with larger members having more of all resources, but correspondingly more expensive. While the designer can fairly easily count how many gates and I/Os pins are needed, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. (For example, a [[crossbar switch]] requires much more routing than a [[systolic array]] with the same gate count.) Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, gate array manufacturers try to provide just enough tracks so that most designs that will fit in terms of gates and I/O pins can be routed. This is determined by estimates such as those derived from [[Rent's rule]] or by experiments with existing designs.

The main drawbacks of gate arrays are their somewhat lower density and performance compared with other approaches to ASIC design. However, this style is often a viable approach for low production volumes.

== Uses ==

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Gate arrays were used widely in the [[home computer]]s in the early to mid 1980s, including in the [[ZX81]], [[ZX Spectrum]], [[BBC Micro]], [[Acorn Electron]], [[Advance 86]], and Commodore [[Amiga]].

In the 1980s, the Forth [[RTX2010|Novix N4016]] and [[HP 3000]] Series 37 CPUs, both [[stack machine]]s were implemented by gate arrays as were some graphic terminal functions.<ref>{{cite journal |first=F.C. |last=Amerson |title=Simplicity in a Microcoded Computer Architecture |journal=Hewlett Packard Journal |volume=36 |issue=9 |pages=7–12 |date=September 1985 |url=https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1985-09.pdf |quote=The Series 37 CPU chip is a CMOS gate array using nearly 8000 gates.}}</ref><ref>{{cite journal |first1=J.E. |last1=Watkins |first2=P.A. |last2=Brown |first3=G. |last3=Szeman |first4=S.E. |last4=Carrie |title=Hardware Design of the HP 150 Personal Computer...it's really two products — a computer and a terminal |journal=Hewlett Packard Journal |volume=35 |issue=8 |pages=25–30 |date=August 1984 |url=https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1984-08.pdf |quote=To reduce the IC count on the video card, a PLA (programmable logic array) and a TTL gate array are used. The gate array implements most of the circuitry of the graphics controller section, including control of the RAM. Compared to discrete circuitry, the gate array consumes one fifth the space, one fourth the power, and one half the cost.}}</ref> Some supporting hardware in at least 1990s [[VAX_7000_and_VAX_10000VAX 7000 and VAX 10000|DEC]] and [[HP_9000HP 9000#S/X-class|HP]] servers was implemented by gate arrays.<ref>{{cite journal |last1=Allison |first1=B.R. |last2=Van Ingen |first2=C. |title=Technical description of the DEC 7000 and DEC 10000 AXP family |journal=Digital Technical Journal |volume=4 |issue=4 |pages=100– |date=1992 |doi= |url=https://www.linux-mips.org/pub/linux/mips/people/macro/DEC/DTJ/DTJ806/DTJ806PF.PDF |quote=All modules utilize LSI Logic LCA100K series gate arrays for the system bus interface and for on-board logic functions. The LSI Logic LCA100K features up to 235K two-input NAND gates. All modules use the same custom I/O driver circuit within their respective gate arrays to drive and receive the system bus. A custom 419-pin pin grid array (PGA) package was developed to house all bus interface gate arrays. ... A minimal DEC 7000 system includes 430,000 gates of logic contained in gate arrays, whereas a minimal [[VAX_6000VAX 6000#VAX_6000_Model_2x0VAX 6000 Model 2x0|VAX 6000 Model 200]] includes 94,000 gates.}}</ref><ref>{{cite journal |last1=Bening |first1=L.C. |last2=Brewer |first2=T.M. |last3=Foster |first3=H.D. |last4=Quigley |first4=J.S. |last5=Sussman |first5=R.A. |last6=Vogel |first6=P.F. |last7=Wells |first7=A.W. |title=Physical Design of 0.35-μm Gate Arrays for Symmetric Multiprocessing Servers |journal=Hewlett-Packard Journal |volume=48 |issue=2 |pages=95–103 |date=1997 |doi= |url=https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1997-04.pdf |quote=The PA 8000s will initially run at 180 MHz, with the rest of the system running at 120 MHz. Except for the [[PA-8000|PA 8000]] and associated SRAMs and DRAMs, the bulk of the system logic is implemented in Fujitsu CG61 0.35-μm gate arrays, as shown in Table I. (Processor Interface, Crossbar, Memory Interface, Node-to-Node Interface) One additional gate array is implemented in the much less expensive CG51 0.5-μm process. (I/O Interface)}}</ref>

==References==

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;Databooks

{{refbegin}}

* {{cite book |chapter=3. Uncommitted Logic Arrays |title=Quick Reference Guide: Discrete Semiconductors, Integrated Circuits, Power Mosfets |publisher=Ferranti Semiconductoras |via=Bitsavers.org |date=1983 |pages=147– |url=http://www.bitsavers.org/components/ferranti/1983_Ferranti_Quick_Reference_Guide.pdf}}

* {{cite book |title=TGC100 Series 1-μm CMOS Gate Arrays Data Sheet |publisher=Texas Instruments |via=BitSavers.org |date=1988 |id=SRG006A |url=http://www.bitsavers.org/components/ti/gate-array/TGC100_Series_1-um_CMOS_Gate_Arrays_Data_Sheet_198810.pdf}}

* {{cite book |title=Channelless Gate Arrays: 1990 Data Book and Design Evaluation Guide |date=1990 |via=Bitsavers.org |publisher=Fujitsu |url=http://www.bitsavers.org/components/fujitsu/_dataBooks/1990_Fujitsu_Channelless_Gate_Arrays.pdf}}

* {{cite book |title=CMOS Channeled Gate Arrays: 1991 Data Book and Design Evaluation Guide |date=1991 |via=Bitsavers.org |publisher=Fujitsu |url=http://www.bitsavers.org/components/fujitsu/_dataBooks/1991_Fujitsu_CMOS_Channeled_Gate_Arrays.pdf}}

* {{cite book |chapter=Array Based ASICS |pages=41–54 |title=Short Form Catalog 1991 |publisher=LSI Logic |via=Bitsavers.org |date=1991 |url=http://www.bitsavers.org/components/lsiLogic/_dataBooks/1991_LSI_Logic_Short_Form_Catalog.pdf |id=13000}}

{{refend}}

== External links ==

* {{Commons category-inline|Gate arrays}}

* {{cite web |first=Ken |last=Shirriff |title=Inside an unusual 7400-series chip implemented with a gate array |date=March 2024 |url=http://www.righto.com/2024/03/idt-gate-array.html}}

[[Category:Gate arrays| ]]