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Atmel AVR instruction set: Difference between revisions

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{{Short description|Microcontroller machine language}}
{{manual|date=June 2014}}
{{main article|Atmel AVR}}
 
Line 94 ⟶ 93:
| style="text-align:center;" colspan="8"| R27
| style="text-align:center;" colspan="8"| R26
| style="background:white; color:black;"| '''ZX''' (pointer)
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="6"|  
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|- style="background:silver;color:black"
| style="text-align:center;" colspan="22"| PC
| style="background:white; color:black;"| [[Program counter|'''P'''rogram '''C'''counterounter]]
|-
|colspan="21" | '''Extended memory''' <br />
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===Status register===
The status register bits are:
#<li value=0> C [[Carry flag]]. This is a borrow flag on subtracts.</li>
#<li value=0> C [[Carry flag]]. This is a borrow flag on subtracts. The <code>INC</code> and <code>DEC</code> instructions do ''not'' modify the carry flag, so they may be used to loop over multi-byte arithmetic operations.<ref name="isa_manual">{{cite web |url=http://ww1.microchip.com/downloads/en/devicedoc/atmel-0856-avr-instruction-set-manual.pdf |title=AVR Instruction Set Manual |date=November 2016 |publisher=Atmel |id=Atmel-0856L}}</ref></li>
# Z [[Zero flag]]. Set to 1 when an arithmetic result is zero, and cleared when it is non-zero.
# N [[Negative flag]]. Set to a copy of the most significant bit of an arithmetic result.
# V [[Overflow flag]]. Set in case of two's complement overflow.
# S Sign flag. Unique to AVR, this is always N⊕VN[[Exclusive or|⊕]]V, and shows the true sign of a comparison.
# H [[Half-carry flag]]. This is an internal carry from additions and is used to support [[Binary-coded decimal|BCD]] arithmetic.
# T Bit copy. Special bit load and bit store instructions use this bit.
# I [[Interrupt flag]]. Set when interrupts are enabled.
 
There are two special cases which exist to facilitate multi-byte arithmetic:
* The <code>INC</code> and <code>DEC</code> instructions do ''not'' modify the carry flag, so they may be used to loop over [[arbitrary-precision arithmetic]] operands.<ref name="isa_manual">{{cite web |url=https://ww1.microchip.com/downloads/en/DeviceDoc/AVR-InstructionSet-Manual-DS40002198.pdf |title=AVR Instruction Set Manual |date=November 2016 |publisher=Atmel |id=Atmel-0856L}}</ref>{{Rp|84,101}}
* The <code>CPC</code>, <code>SBC</code> and <code>SBCI</code> (compare/subtract with carry) instructions do ''not'' set the Z flag when the result is zero, but only clear it if the result is non-zero.{{r|isa_manual|p=79,147,149}} For ''fixed'' precision multi-byte comparisons, implemented with an [[Loop unrolling|unrolled]] <code>CP; CPC; CPC; CPC</code> sequence, this produces a zero flag which is set only if the ''entire'' difference is zero.
 
== Addressing ==
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* D16 is a 16-bit data address covering 64&nbsp;[[KiB]]; in parts with more than 64&nbsp;KiB data space, the contents of the RAMPD segment register is prepended
* P22 is a 22-bit program address covering 2<sup>22</sup> 16-bit words (i.e. 8&nbsp;[[MiB]])
* S7 and S12 are 7-bit (resp.and 12-bit) ''signed'' displacements, in units of words, relative to the program address stored in the program counter
 
{| class="wikitable"
|+ AVR instruction set
|-
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! Transfer
! Jump
|-
! Branch
|valign=top rowspan=5|{{#tag:syntaxhighlight|
ADD Rd, Rr
ADC Rd, Rr
ADIW Rp+1:Rp, K6
 
SUB Rd, Rr
SUBI Rdh, K8
SBC Rd, Rr
SBCI Rdh, K8
SBIW Rp+1:Rp, K6
 
INC Rd
DEC Rd
 
AND Rd, Rr
ANDI Rdh, K8
OR Rd, Rr
ORI Rdh, K8
<!--
<S> CLR Rd </S> (EOR)
<S> SER Rdh </S> (LDI)
<S> SBR Rdh, K8 </S> (ORI)
<S> CBR Rdh, K8 </S> (ANDI)
<S> TST Rd </S> (AND)
!-->
COM Rd
NEG Rd
CP Rd, Rr
CPC Rd, Rr
CPI Rdh, K8
SWAP Rd
<!--
<S> LSL Rd </S> (ADD)
<S> ROL Rd </S> (ADC)
!-->
LSR Rd
ROR Rd
ASR Rd
 
MUL Rd, Rr
MULS Rdh, Rrh
MULSU Rdq, Rrq
FMUL Rdq, Rrq
FMULS Rdq, Rrq
FMULSU Rdq, Rrq
|lang="nasm"|style=font-size:95%}}
|valign=top rowspan=5|{{#tag:syntaxhighlight|
BSET s
BCLR s
SBI IO5, b
CBI IO5, b
BST Rd, b
BLD Rd, b
 
NOP
BREAK
SLEEP
WDR|lang="nasm"|style=font-size:95%}}
|valign=top rowspan=5|{{#tag:syntaxhighlight|
MOV Rd, Rr
MOVW Rd+1:Rd, Rr+1:Rr
 
IN Rd, IO6
OUT IO6, Rr
 
PUSH Rr
POP Rr
 
LDI Rdh, K8
LDS Rd, D16
 
LD Rd, X
LDD Rd, YZ+K6
LD Rd, -XYZ
LD Rd, XYZ+
 
STS D16, Rr
 
ST X, Rr
STD YZ+K6, Rr
ST -XYZ, Rr
ST XYZ+, Rr
 
LPM
LPM Rd, Z
LPM Rd, Z+
ELPM
ELPM Rd, Z
ELPM Rd, Z+
 
SPM|lang="nasm"|style=font-size:95%}}
|valign=top|{{#tag:syntaxhighlight|
RJMP S12
IJMP
EIJMP
JMP P22|lang="nasm"|style=font-size:95%}}
|-
! Call
|-
|valign=top|{{sxhl|2=nasm#tag:syntaxhighlight|
RCALL S12
ADD Rd, Rr
ICALL
ADC Rd, Rr
EICALL
ADIW Rp+1:Rp, K6
CALL P22
 
SUB Rd, Rr
RET
SUBI Rdh, K8
RETI|lang="nasm"|style=font-size:95%}}
SBC Rd, Rr
|-
SBCI Rdh, K8
! Branch
SBIW Rp+1:Rp, K6
|-
|valign=top|{{#tag:syntaxhighlight|
INC Rd
CPSE Rd, Rr
DEC Rd
 
SBRC Rr, b
AND Rd, Rr
SBRS Rr, b
ANDI Rdh, K8
 
OR Rd, Rr
SBIC IO5, b
ORI Rdh, K8
SBIS IO5, b
}} <!--
 
<S> CLR Rd </S> (EOR)
BRBC s, S7
<S> SER Rdh </S> (LDI)
BRBS s, S7|lang="nasm"|style=font-size:95%}}
<S> SBR Rdh, K8 </S> (ORI)
<S> CBR Rdh, K8 </S> (ANDI)
<S> TST Rd </S> (AND)
!-->
{{sxhl|2=nasm|
COM Rd
NEG Rd
CP Rd, Rr
CPC Rd, Rr
CPI Rdh, K8
SWAP Rd
}} <!--
<S> LSL Rd </S> (ADD) !-->
LSR Rd <!--
<S> ROL Rd </S> (ADC) !-->
ROR Rd
ASR Rd
{{sxhl|2=nasm|
MUL Rd, Rr
MULS Rdh, Rrh
MULSU Rdq, Rrq
FMUL Rdq, Rrq
FMULS Rdq, Rrq
FMULSU Rdq, Rrq
}}
|valign=top|{{sxhl|2=nasm|
BSET s
BCLR s
SBI IO5, b
CBI IO5, b
BST Rd, b
BLD Rd, b
NOP
BREAK
SLEEP
WDR
}}
|valign=top|{{sxhl|2=nasm|
MOV Rd, Rr
MOVW Rd+1:Rd, Rr+1:Rr
IN Rd, IO6
OUT IO6, Rr
PUSH Rr
POP Rr
LDI Rdh, K8
LDS Rd, D16
LD Rd, X
LDD Rd, YZ+K6
LD Rd, -XYZ
LD Rd, XYZ+
STS D16, Rr
ST X, Rr
STD YZ+K6, Rr
ST -XYZ, Rr
ST XYZ+, Rr
LPM
LPM Rd, Z
LPM Rd, Z+
ELPM
ELPM Rd, Z
ELPM Rd, Z+
SPM
}}
|valign=top|{{sxhl|2=nasm|
RJMP S12
IJMP
EIJMP
JMP P22
}}
|valign=top|{{sxhl|2=nasm|
CPSE Rd, Rr
SBRC Rr, b
SBRS Rr, b
SBIC IO5, b
SBIS IO5, b
BRBC s, S7
BRBS s, S7
}}
|valign=top|{{sxhl|2=nasm|
RCALL S12
ICALL
EICALL
CALL P22
RET
RETI
}}
|}
 
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! scope=row | Minimal AVR1 Core
| {{ublist|AT90S1200|ATtiny11|ATtiny12|ATtiny15|ATtiny28}}
| {{ublist|item_style=font-family:monospace;|ADD (LSL)|ADC (ROL)|SUB |SUBI|SBC|SBCI|AND (TST)|ANDI (CBR)|OR|ORI (SBR)|EOR (CLR)|COM|NEG|SBR|CBR|INC|DEC|TST|CLR|SER}}
| {{ublist|item_style=font-family:monospace;|RJMP|RCALL|RET|RETI|CPSE|CP|CPC|CPI|SBRC|SBRS|SBIC|SBIS|BRBS (BRCS,&ZeroWidthSpace;BRLO,&ZeroWidthSpace;BREQ,&ZeroWidthSpace;BRMI,&ZeroWidthSpace;BRVS,&ZeroWidthSpace;BRLT,&ZeroWidthSpace;BRHS,&ZeroWidthSpace;BRTS,&ZeroWidthSpace;BRIE)|BRBC|BREQ|BRNE|BRCS| (BRCC|,&ZeroWidthSpace;BRSH|BRLO|BRMI|,&ZeroWidthSpace;BRNE,&ZeroWidthSpace;BRPL|,&ZeroWidthSpace;BRVC,&ZeroWidthSpace;BRGE|BRLT|BRHS|,&ZeroWidthSpace;BRHC|BRTS|,&ZeroWidthSpace;BRTC|BRVS|BRVC|BRIE|,&ZeroWidthSpace;BRID)}}
| {{ublist|item_style=font-family:monospace;|LD|ST|MOV|LDI (SER)|IN|OUT|{{mono|LPM}} (not in AT90S1200)|item7_style=font-family:unset;}}
| {{ublist|item_style=font-family:monospace;|SBI|CBI|LSL|LSR|ROL|ROR|ASR|SWAP|BSET (SEC, SEZ, SEN, SEV, SES, SEH, SET, SEI)|BCLR|BST|BLD|SEC| (CLC|SEN|, CLZ, CLN|SEZ|CLZ|SEI|CLI|SES|, CLV, CLS|SEV|CLV|SET|, CLH, CLT, CLI)|SEHBST|CLHBLD|NOP|SLEEP|WDR}}
|- style="vertical-align:top;"
! scope=row | Classic Core up to 8K Program Space ("AVR2")
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== Instruction encoding ==
Bit assignments:
* {{not a typo|rrrrr / ddddd}} = Source/destination register
* {{not a typo|rrrr / dddd}} = Source/destination register (R16–R31)
* {{not a typo|rrr / ddd}} = Source/destination register (R16–R23)
* RRRR / DDDD = Source/destination register pair (R1:R0–R31:R30)
* {{not a typo|ddddd}} = Destination register
* {{not a typo|dddd}} = Destination register (R16–R31)
* {{not a typo|ddd}} = Destination register (R16–R23)
* DDDD = Destination register pair (R1:R0–R31:R30)
* pp = Register pair, W, X, Y or Z
* y = Y/Z register pair bit (0=Z, 1=Y)
* u = FMUL(SFMULS(U)) signedunsigned withbit (0=FMULS signed or, 1=FMULSU unsigned)
* s = Store/load bit (0=loadLD Rd,mem, 1=storeST mem,Rd)
* c = Call/jump (0=jump, 1=call)
* cy = With carry (0=without carry, 1=with carry)
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* {{not a typo|KKKKKKKK}} = 8-bit constant
 
The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The load/storemost withcommonly offsetencountered instructions areis the 5-bit source register field in bits 9 and 3–0. The most extreme example whereis the load/store with offset instructions, which break a 6-bit offset is broken into three pieces.
 
{|class="wikitable" style="text-align:center"
Line 586 ⟶ 584:
| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||colspan=3| d d d || u ||colspan=3| r r r ||align=left| FMULS(U) Rd,Rr
|-
|colspan=17|
! 0 || 0 ||colspan=4| opcode || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| 2-operand instructions
|-
! 0 || 0 ||colspan=4| opcode || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| Two-operand instructions
|-
| 0 || 0 || 0 || c̅y̅ || 0 || 1 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| CPC/CP Rd,Rr
Line 624:
! 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d ||colspan=4| opcode ||align=left| Load/store operations
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 0 || 0 || 0 || 0 ||align=left rowspan=2| LDS rdRd,i/STS i,rdRd
|-
| colspan=16| 16-Bit immediate SRAM address i
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 1 || 0 || 0 || 0 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 0 || 1 ||align=left| LD/ST Rd through Z+/Y+
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 1 || 0 ||align=left| LD/ST Rd through &minus;Z/&minus;Y
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 1 || 1 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 0 ||colspan=5| d d d d d || 0 || 1 || q || 0 ||align=left| LPM/ELPM Rd,Z
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| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 0 ||align=left| RETI
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=2| 0 ||≠ 100 || x || 1 || 0 || 0 || 0 || (reserved)
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || 1 || x || x || 1 || 0 || 0 || 0 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||align=left| SLEEP
Line 705 ⟶ 707:
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || c || 0 || 0 || 0 || e || 1 || 0 || 0 || 1 ||align=left| Indirect jump/call to Z or EIND:Z
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || c ||colspan=3| ≠ 000 || e || 1 || 0 || 0 || 1 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 1 || 0 || 1 || 0 ||align=left| DEC Rd
Line 752 ⟶ 756:
**[https://web.archive.org/web/20050714015338/http://users.rcn.com/rneswold/avr/ A GNU Development Environment for the AVR Microcontroller] by Rich Neswold
**[https://gcc.gnu.org/onlinedocs/gcc-3.3.5/gcc/AVR-Options.html AVR Options] in GCC-AVR
*[http://starlo.org/blake/boardmicro/ AVR Instruction Set Simulator (ATmega32u4 for GCC Intel Hex Files)]
*[https://github.com/avr-llvm/architecture/blob/master/Instructions/inheritance.md AVR Instruction Set Inheritance] (LLVM note), based on this page and GCC & Binutils code
 
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