Reconfigurable computing: Difference between revisions

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{{Use American English|date = April 2019}}

{{Short description|Computer architecture that can be reprogrammed}}

{{Use American English|date = April 2019}}

{{Technical|date=May 2009}}

'''Reconfigurable computing''' is a [[computer architecture]] combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computinghardware fabricsplatforms like [[FPGA|field-programmable gate array]]s (FPGAs). The principal difference when compared to using ordinary [[microprocessor]]s is the ability to makeadd substantialcustom changescomputational toblocks theusing [[datapath]] itself in addition to the control flowFPGAs. On the other hand, the main difference from custom hardware, i.e. [[application-specific integrated circuit]]s (ASICs) is the possibility to adapt the hardware during runtime by "loading" a new circuit on the reconfigurable fabric, thus providing new computational blocks without the need to [[Semiconductor device fabrication|manufacture]] and add new [[Integrated circuit|chips]] to the existing system.

==History==

The concept of reconfigurable computing has existed since the 1960s, when [[Gerald Estrin]]'s paper proposed the concept of a computer made of a standard processor and an array of "reconfigurable" hardware.<ref name="Estrin2002">{{cite journal | last1 = Estrin | first1 = G | year = 2002 | title = Reconfigurable computer origins: the UCLA fixed-plus-variable (F+V) structure computer | journal = IEEE Ann. Hist. Comput. | volume = 24 | issue = 4| pages = 3–9 | doi = 10.1109/MAHC.2002.1114865 | s2cid = 7923912 }}</ref><ref>

Estrin, G., "Organization of Computer Systems—The Fixed Plus Variable Structure Computer",

''Proc. Western Joint Computer Conf.'', Western Joint Computer Conference, New York, 1960, pp. 33–40.</ref> The main processor would control the behavior of the reconfigurable hardware. The latter would then be tailored to perform a specific task, such as [[image processing]] or [[pattern matching]], as quickly as a dedicated piece of hardware. Once the task was done, the hardware could be adjusted to do some other task. This resulted in a hybrid computer structure combining the flexibility of software with the speed of hardware.

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===Computer emulation ===

[[File:FPGARetrocomputing.jpg|An FPGA board is being used to recreate the Vector-06C computer.|thumb]]

With the advent of affordable FPGA boards, students' and hobbyists' projects seek to recreate [[vintage computer]]s or implement more novel architectures.<ref name="apple">{{cite web|url=https://www.cs.columbia.edu/~sedwards/apple2fpga/|title=Apple2 FPGA|access-date=6 Sep 2012

}}</ref><ref name="risc">{{cite web|url=http://www.inf.ethz.ch/personal/wirth/Articles/Miscellaneous/RISC.pdf |title=The Design of a RISC Architecture and its Implementation with an FPGA |author=Niklaus Wirth |access-date=6 Sep 2012 }}{{dead link|date=June 2016|bot=medic}}{{cbignore|bot=medic}}</ref><ref name="soc">{{cite web|author=Jan Gray

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=== Intel ===

[[Intel]]<ref name="intel_altera">{{cite web |url=https://newsroom.intel.com/news-releases/intel-completes-acquisition-of-altera/ |title=Intel completes acquisition of Altera |work=Intel Newsroom |access-date=15 November 2016}}</ref> supports partial reconfiguration of their FPGA devices on 28&nbsp;nm devices such as Stratix V,<ref name="stratixv_pr">{{cite web |url=https://www.altera.com/products/fpga/features/stxv-part-reconfig.html |title=Stratix V FPGAs: Ultimate Flexibility Through Partial and Dynamic Reconfiguration |access-date=15 November 2016}}</ref> and on the 20&nbsp;nm Arria 10 devices.<ref name="arria10_pr">{{cite web |url=https://www.altera.com/products/design-software/fpga-design/quartus-prime/features.html |title=Intel Quartus Prime Software Productivity Tools and Features |access-date=15 November 2016}}</ref> The Intel FPGA partial reconfiguration flow for Arria 10 is based on the hierarchical design methodology in the Quartus Prime Pro software where users create physical partitions of the FPGA that can be reconfigured<ref name="arria10_pr_docs">{{cite web |url=https://www.altera.com/en_US/pdfs/literature/hb/qts/qts-qps-5v1.pdf |title=Quartus Prime Standard Edition Handbook Volume 1: Design and Synthesis |publisher=Intel |access-date=15 November 2016 |pages=4–1}}</ref> at runtime while the remainder of the design continues to operate. The Quartus Prime Pro software also support hierarchical partial reconfiguration and simulation of partial reconfiguration.

== Classification of systems ==

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* T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, "Reconfigurable Computing: Architectures and Design Methods", IEEE Proceedings: Computer & Digital Techniques, Vol. 152, No. 2, March 2005, pp.&nbsp;193–208.

* A. Zomaya (editor): Handbook of Nature-Inspired and Innovative Computing: Integrating Classical Models with Emerging Technologies; Springer Verlag, 2006

* J. M. Arnold and D. A. Buell, "VHDL programming on Splash 2," in More FPGAs, Will Moore and Wayne Luk, editors, Abingdon EE & CS Books, Oxford, England, 1994, pp.&nbsp;182–191. (Proceedings, International Workshop on Field-Programmable Logic, Oxford, 1993.)

* J. M. Arnold, D. A. Buell, D. Hoang, D. V. Pryor, N. Shirazi, M. R. Thistle, "Splash 2 and its applications, "Proceedings, International Conference on Computer Design, Cambridge, 1993, pp. 482–486.

* D. A. Buell and Kenneth L. Pocek, "Custom computing machines: An introduction," [[The Journal of Supercomputing]], v. 9, 1995, pp.&nbsp;219–230.

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* [https://web.archive.org/web/20160306094104/http://vlsi-world.com/content/view/48/47 Introduction to Dynamic Partial Reconfiguration]

* [http://www12.informatik.uni-erlangen.de/research/recobus/ ReCoBus-Builder project for easily implementing complex reconfigurable systems]

* [http://www.dresd.org/ DRESD (Dynamic Reconfigurability in Embedded System Design) research project] {{Webarchive|url=https://web.archive.org/web/20080715053642/http://www.dresd.org/ |date=2008-07-15 }}

{{Programmable Logic}}