Memory segmentation: Difference between revisions

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{{Short description|The divisionDivision of computer's primary memory into separately relocatable segments or sections}}

{{About|segmented computer memory|segments in object code|Object file}}

{{Use dmy dates|date=July 2022|cs1-dates=y}}

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==History==

The [[Burroughs Corporation]] [[Burroughs large systems|B5000]] computer was one of the first to implement segmentation, and "perhaps the first commercial computer to provide virtual memory"<ref>{{cite web |last=Mayer |first=Alastair J. W. |title=The Architecture of the Burroughs B5000 - 20 Years Later and Still Ahead of the Times? |url=http://www.smecc.org/The%20Architecture%20%20of%20the%20Burroughs%20B-5000.htm |access-date=2012-03-15}}</ref> based on segmentation. The B5000 is equipped with a segment information table called the Program Reference Table (PRT) which is used to indicate whether the corresponding segment resides in the main memory, to maintain the [[base address]] and the size of the segment.<ref>{{cite book |title=Computer Architecture and Organization |last=HAYESHayes |first=JOHNJohn P. |isbn=0-07-027363-4 |year=1978 |ppage=371|publisher=McGraw-Hill }}</ref> The later [[Burroughs large systems#B6500|B6500]] computer also implemented segmentation; a version of its architecture is still in use today on the Unisys ClearPath Libra servers.{{Citation needed|date=April 2024}}

The [[GE-600 series|GE-645]] computer, a modification of the [[GE-600 series|GE-635]] with segmentation and paging support added, was designed in 1964 to support [[Multics]].

The [[Intel iAPX 432]],<ref>{{cite book |publisher=Intel Corporation |title=Introduction to the IAPX 432 Architecture |date=1981 |pages=78 |url=http://bitsavers.org/components/intel/iAPX_432/171821-001_Introduction_to_the_iAPX_432_Architecture_Aug81.pdf}}</ref> begun in 1975, attempted to implement a true segmented architecture with memory protection on a microprocessor.

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==Examples==

===[[Burroughs Large Systems|Burroughs large system architectures]]===

{{seealso|Burroughs large systems descriptors}}

Burroughs introduced segmentation on the [[B5000]], followed by the compatible B5500 and B5700.

The later [[B6500]] replaced the Program Reference Table (PRT) with a [[Saguaro stack]], changed control word formats, changed [[Burroughs large systems descriptors|descriptor]] formats and changed the mechanism for referring to a control word or descriptor.

====B5000, B5500 and B5700====

{{see also|B5000 instruction set|Burroughs large systems descriptors#B5000, B5500 and B5700}}

Words in the [[Burroughs Large Systems#B5000, B5500, and B5700|B5000, B5500 and B5700]] are 48 bits long.<ref name=oper>{{Citation

| title = The Operational Characteristic of the Processors for the Burroughs B 5000

| id = 5000-21005A

| edition = A

| year = 1962

| url = https://bitsavers.org/pdf/burroughs/LargeSystems/B5000_5500_5700/5000-21005_B5000_operChar_1963.pdf

| ___location = Detroit

| publisher = Burroughs

}}

</ref> [[Burroughs large systems descriptors|Descriptors]] have the uppermost bit set in the word. They reside in either the Program Reference Table (PRT) or the stack, and contain a ''presence bit'' indicating whether the data are present in memory. There are distinct data and program descriptors.<ref name=oper />{{rp|pages = 4{{hyp}}2-4{{hyp}}4}}

====B6500, B7500 and successors====

{{see also|Burroughs B6x00-7x00 instruction set|Burroughs large systems descriptors#B6500, B7500 and successors}}

Words in the B6500 and its successors have 48 bits of data and 3 tag bits.<!--4 bits in later machines?--><ref name="b6500-ref-man">{{cite book |url=http://www.bitsavers.org/pdf/burroughs/LargeSystems/B6500_6700/1043676_B6500_RefMan_Sep69.pdf |title=B6500 Information Processing Systems Reference Manual |publisher=Burroughs |date=September 1969}}</ref>{{rp|page=2{{hyp}}1}} The tag bits indicate the type of data contained in the word; there are several descriptor types, indicated by different tag bit values.<ref name="b6500-ref-man" />{{rp|pages=6{{hyp}}5-6{{hyp}}10}} Control words and descriptors reside in the Saguaro stack. Array segments may be paged.

The line includes the B6500, B6700, B7700, B6800, B6900, B5900, the A-series Burroughs and Unisys machines, and the current Clearpath MCP systems (Libra). While there have been a few enhancements over the years, particularly hardware advances, the architecture has changed little. The segmentation scheme has remained the same, see [[Virtual Memory#Segmented_virtual_memory|Segmented memory]].

===Multics architectures===

{{stub-section|date=January 2024}}

===S/370 architecture===

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|date=September 1974

|pages=57–68

|workseries=Systems

|publisher=[[IBM]]

|section=Dynamic Address Translation

|section-url=http://www.bitsavers.org/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf#page=57

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The [[Intel 80286]] and later processors add "286 [[protected mode]]", which retains 16-bit addressing, and adds segmentation (without paging) and per-segment memory protection. For backward compatibility, all x86 CPUs start up in "real mode", with the same fixed overlapping 64&nbsp;KiB segments, no memory protection, only 1&nbsp;MiB physical address space, and some subtle differences ([[high memory area]], [[unreal mode]]). In order to use its full 24-bit (16&nbsp;MiB) physical address space and advanced [[memory management unit|MMU]] features, an 80286 or later processor must be switched into "protected mode" by software, usually the operating system or a [[DOS extender]]. If a program does not use the segment registers, or only puts values into them that it receives from the operating system, then identical code can run in real mode or protected mode, but most real-mode software computes new values for the segment registers, breaking this compatibility.

The [[Intel i386]] and later processors add "386 [[protected mode]]", which uses 32-bit addressing, retains segmentation, and adds [[memory paging]]. In these processors, the segment table, rather than pointing to a page table for the segment, contains the segment address in ''linear memory''. When paging is enabled, addresses in linear memory are then mapped to physical addresses using a separate page table. Most operating systems did not use the segmentation capability, despite possible advantages (4 x 4GiB logical address space instead of only 4 GiB), opting to keep the base address in all segment registers equal to 0 at all times and provide per-page memory protection and swapping using only paging. Some use the CS register to provide [[executable space protection]] on processors lacking the [[NX bit]] or use the FS or GS registers to access thread-local storage.<ref name="pietrek-windows-nt">{{cite web |url=https://learn.microsoft.com/en-us/archive/msdn-magazine/2006/may/x64-starting-out-in-64-bit-windows-systems-with-visual-c |title=Everything You Need To Know To Start Programming 64-Bit Windows Systems |publisher=Microsoft |author=Matt Pietrek |author-link=Matt Pietrek |date=May 2006 |access-date=April 18, 2023}}</ref><ref name="drepper-linux-etc">{{cite web |url=http://www.akkadia.org/drepper/tls.pdf |title=ELF Handling For Thread-Local Storage |first=Ulrich |last=Drepper |date=August 22, 2013}}</ref>

The [[x86-64]] architecture does not support segmentation in "[[long mode]]" (64-bit mode).<ref name=":1">{{cite book |title=AMD64 Technology AMD64 Architecture Programmer's Manual Volume 2: System Programming |publisher=Advanced Micro Devices |volume=2 |date=2018 |url=https://www.amd.com/system/files/TechDocs/24594.pdf}}</ref> Four of the segment registers: CS, SS, DS, and ES are forced to 0, and the limit to 2⁶⁴. The segment registers FS and GS can still have a nonzero base address. This allows operating systems to use these segments for special purposes such as thread-local storage.<ref name="pietrek-windows-nt" /><ref name="drepper-linux-etc" />