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{{short description|
{{About|a technical explanation of the architecture of the [[UniPro]] protocol stack|an overview of the protocol stack, its purpose, usage and status|UniPro}}
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Versions 1.0 and 1.1 of UniPro use MIPI's [[D-PHY]] technology for the off-chip Physical Layer. This PHY allows inter-chip communication. Data rates of the D-PHY are variable, but are in the range of 500-1000 Mbit/s (lower speeds are supported, but at decreased power efficiency). The D-PHY was named after the Roman number for 500 ("D").
The [[D-PHY]]<ref>[https://members.mipi.org/mipi-adopters/file-fix/Specifications/Board%20Approved/mipi_D-PHY_specification_v01-00-00.pdf MIPI Alliance Specification for D-PHY v1.00.00] {{Webarchive|url=https://web.archive.org/web/20110727084541/https://members.mipi.org/mipi-adopters/file-fix/Specifications/Board%20Approved/mipi_D-PHY_specification_v01-00-00.pdf |date=2011-07-27 }}, requires an account at the MIPI website</ref> uses differential signaling to convey PHY symbols over micro-stripline wiring. A second differential signal pair is used to transmit the associated clock signal from the source to the destination. The D-PHY technology thus uses a total of 2 clock wires per direction plus 2 signal wires per lane and per direction. For example, a D-PHY might use 2 wires for the clock and 4 wires (2 lanes) for the data in the forward direction, but 2 wires for the clock and 6 wires (3 lanes) for the data in the reverse direction. Data traffic in the forward and reverse directions are totally independent at this level of the protocol stack.
In UniPro, the D-PHY is used in a mode (called "8b9b" encoding) which conveys 8-bit bytes as 9-bit symbols. The UniPro protocol uses this to represent special control symbols (outside the usual 0 to 255 values). The PHY itself uses this to represent certain special symbols that have meaning to the PHY itself (e.g. IDLE symbols). Note that the ratio 8:9 can cause some confusion when specifying the data rate of the D-PHY: a PHY implementation running with a 450 MHz clock frequency is often rated as a 900 Mbit/s PHY, while only 800 Mbit/s is then available for the UniPro stack.
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==={{Anchor|M-PHY}}M-PHY===
Versions 1.4 and beyond of UniPro support both the [[D-PHY]] as well as [[M-PHY]]<ref>[https://members.mipi.org/mipi-adopters/file-fix/Specifications/Board%20Approved/mipi_M-PHY_specification_v1-00-00.pdf MIPI Specification for M-PHY version 1.00.00] {{Webarchive|url=https://web.archive.org/web/20111007190626/https://members.mipi.org/mipi-adopters/file-fix/Specifications/Board%20Approved/mipi_M-PHY_specification_v1-00-00.pdf |date=2011-10-07 }}, requires an account at the MIPI website</ref> technology. The M-PHY technology is still in draft status, but supports high-speed data rates starting at about 1000 Mbit/s (the M-PHY was named after the Roman number for 1000). In addition to higher speeds, the M-PHY will use fewer signal wires because the clock signal is embedded with the data through the use of industry-standard [[8B/10B encoding|8b10b encoding]]. Again, a PHY capable of transmitting user data at 1000 Mbit/s is typically specified as being in 1250 Mbit/s mode due to the 8b10b encoding.
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