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→Status register: Added Z flag exception for subtract with carry. Reorganized to group it with C flag exception. |
→Status register: Added article link to Exclusive OR function |
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{{Short description|Microcontroller machine language}}
{{main article|Atmel AVR}}
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# N [[Negative flag]]. Set to a copy of the most significant bit of an arithmetic result.
# V [[Overflow flag]]. Set in case of two's complement overflow.
# S Sign flag. Unique to AVR, this is always
# H [[Half-carry flag]]. This is an internal carry from additions and is used to support [[Binary-coded decimal|BCD]] arithmetic.
# T Bit copy. Special bit load and bit store instructions use this bit.
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There are two special cases which exist to facilitate multi-byte arithmetic:
* The <code>INC</code> and <code>DEC</code> instructions do ''not'' modify the carry flag, so they may be used to loop over [[arbitrary-precision arithmetic]] operands.<ref name="isa_manual">{{cite web |url=
* The <code>CPC</code>, <code>SBC</code> and <code>SBCI</code> (compare/subtract with carry) instructions do ''not'' set the Z flag when the result is zero, but only clear it if the result is non-zero.{{r|isa_manual|p=79,147,149}} For ''fixed'' precision multi-byte comparisons, implemented with an [[Loop unrolling|unrolled]] <code>CP; CPC; CPC; CPC</code> sequence, this produces a zero flag which is set only if the ''entire'' difference is zero.
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! Transfer
! Jump
! Branch▼
! Call▼
|-
|valign=top rowspan=5|{{#tag:syntaxhighlight|
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
INC
DEC
AND
ANDI
OR
ORI
<!--
|lang="nasm"|style=font-size:95%}} <!--▼
<S> CLR
<S> SER
<S> SBR
<S> CBR
<S> TST
!-->
{{#tag:syntaxhighlight|▼
SWAP Rd
CPI Rdh, K8▼
<!--
▲SWAP Rd
|lang="nasm"|style=font-size:95%}} <!--▼
<S>
!-->
▲<S> ROL Rd </S> (ADC) !-->
{{#tag:syntaxhighlight|▼
ASR Rd
▲ROR Rd
MULSU Rdq, Rrq
▲ASR Rd
FMUL Rdq, Rrq
FMULS Rdq, Rrq
FMULSU Rdq, Rrq
|lang="nasm"|style=font-size:95%}}
|valign=top rowspan=5|{{#tag:syntaxhighlight|
MUL Rd, Rr▼
|lang="nasm"|style=font-size:95%}}▼
▲BSET s
▲BCLR s
SBI IO5, b▼
CBI IO5, b▼
NOP
BREAK
SLEEP
▲|valign=top rowspan=5|{{#tag:syntaxhighlight|
|lang="nasm"|style=font-size:95%}}▼
MOV Rd, Rr
MOVW Rd+1:Rd, Rr+1:Rr
IN
OUT
PUSH
POP
LDI
LDS
LD
LDD
LD
LD
STS
ST
STD
ST
ST
LPM
LPM
LPM
ELPM
ELPM
ELPM
|lang="nasm"|style=font-size:95%}}▼
|valign=top|{{#tag:syntaxhighlight|
RJMP
IJMP
EIJMP
▲JMP P22|lang="nasm"|style=font-size:95%}}
|-
▲! Call
|-
SBRC Rr, b▼
SBRS Rr, b▼
BRBC s, S7▼
|valign=top|{{#tag:syntaxhighlight|
RCALL
ICALL
EICALL
CALL
RET
▲RETI|lang="nasm"|style=font-size:95%}}
|-
▲! Branch
|-
▲|valign=top|{{#tag:syntaxhighlight|
▲BRBS s, S7|lang="nasm"|style=font-size:95%}}
|}
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== Instruction encoding ==
Bit assignments:
* {{not a typo|rrrrr / ddddd}} = Source/destination register
* {{not a typo|rrrr / dddd}} = Source/destination register (R16–R31)
* {{not a typo|rrr / ddd}} = Source/destination register (R16–R23)
* RRRR / DDDD = Source/destination register pair (R1:R0–R31:R30)
* pp = Register pair, W, X, Y or Z
* y = Y/Z register pair bit (0=Z, 1=Y)
* u =
* s = Store/load bit (0=
* c = Call/jump (0=jump, 1=call)
* cy = With carry (0=without carry, 1=with carry)
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* {{not a typo|KKKKKKKK}} = 8-bit constant
The Atmel AVR uses many split fields, where bits are not contiguous in the instruction word. The
{|class="wikitable" style="text-align:center"
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| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 ||colspan=3| d d d || u ||colspan=3| r r r ||align=left| FMULS(U) Rd,Rr
|-
|colspan=17|
! 0 || 0 ||colspan=4| opcode || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| 2-operand instructions▼
|-
▲! 0 || 0 ||colspan=4| opcode || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left|
|-
| 0 || 0 || 0 || c̅y̅ || 0 || 1 || r ||colspan=5| d d d d d ||colspan=4| r r r r ||align=left| CPC/CP Rd,Rr
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! 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d ||colspan=4| opcode ||align=left| Load/store operations
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || 0 || 0 || 0 || 0 ||align=left rowspan=2| LDS
|-
| colspan=16| 16-Bit immediate SRAM address i
|-bgcolor=lightgray▼
| 1 || 0 || 0 || 1 || 0
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 0 || 1 ||align=left| LD/ST Rd through Z+/Y+
|-
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 1 || 0 ||align=left| LD/ST Rd through −Z/−Y
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 0 || s ||colspan=5| d d d d d || y || 0 || 1 || 1 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 0 || 0 ||colspan=5| d d d d d || 0 || 1 || q || 0 ||align=left| LPM/ELPM Rd,Z
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| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || 0 || 0 || 1 || 1 || 0 || 0 || 0 ||align=left| RETI
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 ||colspan=2|
▲|-bgcolor=lightgray
▲| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || 1 || x || x || 1 || 0 || 0 || 0 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || 1 || 1 || 0 || 0 || 0 || 1 || 0 || 0 || 0 ||align=left| SLEEP
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|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || c || 0 || 0 || 0 || e || 1 || 0 || 0 || 1 ||align=left| Indirect jump/call to Z or EIND:Z
|-bgcolor=lightgray
| 1 || 0 || 0 || 1 || 0 || 1 || 0 || c ||colspan=3| ≠ 000 || e || 1 || 0 || 0 || 1 || (reserved)
|-
| 1 || 0 || 0 || 1 || 0 || 1 || 0 ||colspan=5| d d d d d || 1 || 0 || 1 || 0 ||align=left| DEC Rd
| |||