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#Exclusive read exclusive write (EREW)—every memory cell can be read or written to by only one processor at a time
#Concurrent read exclusive write (CREW)—multiple processors can read a memory cell but only one can write at a time
#Exclusive read concurrent write (ERCW)—mostly never considered because it mostly doesn't add more power<ref>{{Cite journal |last1=MacKenzie |first1=Philip D. |last2=Ramachandran |first2=Vijaya |date=1998-04-06 |title=ERCW PRAMs and optical communication |url=https://www.sciencedirect.com/science/article/pii/S0304397597001990 |journal=Theoretical Computer Science |volume=196 |issue=1 |pages=153–180 |doi=10.1016/S0304-3975(97)00199-0 |issn=0304-3975|url-access=subscription }}</ref>
#Concurrent read concurrent write (CRCW)—multiple processors can read and write. A CRCW PRAM is sometimes called a '''concurrent random-access machine'''.<ref>Neil Immerman, ''[http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.57.1834&rep=rep1&type=pdf Expressibility and parallel complexity]''. SIAM Journal on Computing, vol. 18, no. 3, pp. 625-638, 1989.</ref>
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==External links==
* [http://www-wjp.cs.uni-sb.de/forschung/projekte/SB-PRAM/index.php Saarland University's prototype PRAM] {{Webarchive|url=https://web.archive.org/web/20160303202357/http://www-wjp.cs.uni-sb.de/forschung/projekte/SB-PRAM/index.php |date=2016-03-03 }}
* [http://www.umiacs.umd.edu/users/vishkin/XMT/spaa07paper.pdf University Of Maryland's PRAM-On-Chip prototype]. This prototype seeks to put many parallel processors and the fabric for inter-connecting them on a single chip
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{{Parallel Computing}}
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