Depletion-load NMOS logic: Difference between revisions

Revision as of 19:24, 16 September 2024

Latest revision as of 06:37, 6 August 2025

(5 intermediate revisions by 5 users not shown)

Line 1:

{{short description|Form of digital logic family in integrated circuits}}

[[File:Nmos depletion and.svg|right|thumb|A depletion-load and two enhancement-mode NMOS transistor making up [[NAND gate]].]]

In [[integrated circuit]]s, '''depletion-load NMOS''' is a form of digital [[logic family]] that uses only a single power supply voltage, unlike earlier [[NMOS logic|NMOS]] (n-type [[metal-oxide semiconductor]]) logic families that needed more than one differentmultiple power supply voltagevoltages. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many [[microprocessor]]s and other logic elements.

[[Depletion and enhancement modes|Depletion-mode]] n-type [[MOSFET]]s as load transistors allow single voltage operation and achieve greater speed than possible with pure enhancement-load devices alone. This is partly because the depletion-mode MOSFETs can be a better [[current source]] approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early PMOS and NMOS chips demanded several voltages).

The inclusion of depletion-mode NMOS transistors in the [[Semiconductor device fabrication|manufacturing process]] demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of [[dopant]] in the load transistors channel region, in order to adjust their [[threshold voltage]]. This is normally performed using [[ion implantation]].

Line 13:

{{See also|NMOS logic#History}}

TheFollowing originalthe two typesinvention of MOSFET logic gates, PMOS andthe [[NMOS logic|NMOSMOSFET]], were developed by Frosch and Derick in 1957 at Bell Labs.<ref>{{Cite journal |last=Frosch |first=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of The Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650}}</ref> Following this research, [[Mohamed Atalla|Atalla]] and [[Dawon Kahng|Kahng]] proposedat demonstrated[[Bell aLabs]] workingin MOS1959, devicethey withdemonstrated theirMOSFET Bell Labs teamtechnology in 1960.<ref>{{cite journal |last1name=Atalla |first1=M. |author1-link=Mohamed Atalla |last2=Kahng |first2=D. |author2-link=Dawon Kahng |date=1960 |title=Silicon-silicon dioxide field induced surface devices |journal=IRE-AIEE Solid State Device Research Conference}}</ref><ref"computerhistory">{{cite journal |title=1960 – Metal Oxide Semiconductor (MOS) Transistor Demonstrated |url=https://www.computerhistory.org/siliconengine/metal-oxide-semiconductor-mos-transistor-demonstrated/|title=1960 - Metal Oxide Semiconductor (MOS) Transistor Demonstrated|journal=The Silicon Engine |publisher=[[Computer History Museum]] |access-date=2023-01-16}}</ref> TheirThey team[[Semiconductor included E. E. LaBate and E. I. Povilonis whodevice fabrication|fabricated]] theboth device;[[PMOS M. O. Thurston, L. A. D’Asaro,logic|PMOS]] and J.NMOS R.devices Ligenzawith whoa developed[[10 theμm diffusion processes, and H. K. Gummel and R. Lindner who characterized the device.<ref>process|20{{Citenbsp}}μm journal |last=KAHNG |first=Dprocess]]. |date=1961 |title=Silicon-Silicon Dioxide Surface Device |url=https://doi.org/10.1142/9789814503464_0076 |journal=Technical Memorandum of Bell Laboratories |pages=583–596 |doi=10.1142/9789814503464_0076 |isbn=978-981-02-0209-5}}</ref> However, the NMOS devices were impractical, and only the PMOS type were practical working devices.<ref name="Lojek">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |url=https://archive.org/details/historysemicondu00loje_697 |url-access=limited |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |pages=[https://archive.org/details/historysemicondu00loje_697/page/n327 321]–3}}</ref>

In 1965, [[Chih-Tang Sah]], Otto Leistiko and [[Andrew Grove|A.S. Grove]] at [[Fairchild Semiconductor]] fabricated several NMOS devices with channel lengths between [[10 μm process|8{{nbsp}}μm]] and 65{{nbsp}}μm.<ref>{{cite journal |last1=Sah |first1=Chih-Tang |author1-link=Chih-Tang Sah |last2=Leistiko |first2=Otto |last3=Grove |first3=A. S. |title=Electron and hole mobilities in inversion layers on thermally oxidized silicon surfaces |journal=[[IEEE Transactions on Electron Devices]] |date=May 1965 |volume=12 |issue=5 |pages=248–254 |doi=10.1109/T-ED.1965.15489 |bibcode=1965ITED...12..248L |url=https://pdfslide.net/documents/electron-and-hole-mobilities-in-inversion-layers-on-thermally-oxidized-silicon-57e531d33262d.html|url-access=subscription }}</ref> Dale L. Critchlow and [[Robert H. Dennard]] at [[IBM]] also fabricated NMOS devices in the 1960s. The first IBM NMOS product was a [[memory chip]] with 1{{nbsp}}[[kibibit|kb]] data and 50{{ndash}}100 [[nanosecond|ns]] [[access time]], which entered large-scale manufacturing in the early 1970s. This led to MOS [[semiconductor memory]] replacing earlier [[bipolar junction transistor|bipolar]] and [[ferrite-core memory]] technologies in the 1970s.<ref>{{cite journal |last1=Critchlow |first1=D. L. |title=Recollections on MOSFET Scaling |journal=IEEE Solid-State Circuits Society Newsletter |date=2007 |volume=12 |issue=1 |pages=19–22 |doi=10.1109/N-SSC.2007.4785536 |doi-access=free }}</ref>

===Silicon gate===

Line 40:

===Intel HMOS===

{{redirect|HMOS|operating system|HarmonyOS}}

Intel's own depletion-load NMOS process was known as '''HMOS''', for ''High density, short channel MOS''. The first version was introduced in late 1976 and first used for their [[static RAM]] products,<ref>{{cite journal |first1=A.M. |last1=Volk |first2=P.A. |last2=Stoll |first3=P. |last3=Metrovich |title=Recollections of Early Chip Development at Intel |journal=Intel Technology Journal |volume=5 |issue=Q1 |pages= |date=2001 |url=https://www.intel.com/content/dam/www/public/us/en/documents/research/2001-vol05-iss-1-intel-technology-journal.pdf}}</ref> it was soon being used for faster and/or less power hungry versions of the 8085, 8086, and other chips.