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{{Use dmy dates|date=March 2020|cs1-dates=y}}

{{Machine code}}

In [[computing]], an '''opcode''' (abbreviated from '''operation code''')<ref name="Barron_1978_Opcode"/><ref name="Chiba_2007"/> is an [[enumeration|enumerated value]] that specifies the operation to be performed. Opcodes are employed in hardware devices such as [[arithmetic logic unit]]s (ALUs) and, [[central processing units]] (CPUs), as well as in someand software instruction sets. In ALUs, the opcode is directly applied to circuitry via an input signal bus,. whereasIn contrast, in CPUs, the opcode is the portion of a [[machine code|machine language]] [[instruction (computer science)|instruction]] that specifies the operation to be performed.

==CPUs==

Opcodes are found in the machine language instructions of CPUs as well as in some [[virtual machine#Process virtual machines|abstract computing machines]]. In CPUs, an opcode may be referred to as an '''instruction machine code''',<ref name="Intel_1973_MCS-4"/>, '''instruction code''',<ref name="Intel_1974_MCS-40"/>, '''instruction syllable''',<ref name="Jones_1988_CISC"/><ref name="Domagała_2012"/><ref name="Smotherman_2013"/><ref name="Jones_2016_CISC"/>, '''instruction parcel,''' or '''opstring'''.<ref name="Schulman_2005"/><ref name="Chiba_2007"/>. BesideFor theany opcodeparticular itself,processor most(which instructionsmay alsobe specifya thegeneral dataCPU or a more theyspecialized willprocessing processunit), whichthe opcodes are calleddefined by the processor's [[operandinstruction set architecture]]s (ISA).<ref Opcodesname="Hennessy_2017"/> areThey foundcan inbe thedescribed instructionsusing an [[opcode table]]. The types of CPUsoperations asmay wellinclude as[[arithmetic]], indata somecopying, [[virtuallogical machine#Processoperation]]s, virtualprogram machines|abstractcontrol, computingand machinesspecial instructions (e.g., [[CPUID]]).<ref name="Hennessy_2017"/>

ForIn anyaddition particularto processorthe (whichopcode, maymany beinstructions aspecify generalthe CPUdata or(known aas more[[operand]]s) specializedthe processingoperation unit),will theact opcodesupon, arealthough definedsome byinstructions themay processor'shave [[instructionimplicit setoperands architecture]]or (ISA)none.<ref name="Hennessy_2017"/> Opcodes for a particular ISA can be described by means of an [[opcode table]] which lists details of all possible opcodes. Some instruction sets have nearly uniform fields for opcode and operand specifiers, whereas others (e.g., [[x86]] architecture) have a moreless complicateduniform, variable-length structure.<ref name="Hennessy_2017"/><ref name="Mansfield_1983"/> Instruction sets can be extended through the use of [[opcode prefixesprefix]]es, which add a subset of new instructions made up of existing opcodes following reserved byte sequences.{{Citation needed|date=February 2023}}

===Sample opcode table===

Apart from the opcode itself, an instruction normally also has one or more specifiers for operands on which the operation should act, although some operations may have ''implicit'' operands, or none at all.<ref name="Hennessy_2017"/> Depending on architecture, the operands may be [[processor register|register]] values, values in the [[call stack|stack]], other [[memory]] values, [[I/O]] ports (which may also be [[Memory-mapped I/O|memory mapped]]), etc., specified and accessed using more or less complex [[addressing mode]]s.{{citation needed|date=October 2015}} The types of operations include [[arithmetic]], data copying, [[logical operation]]s, and program control, as well as special instructions (such as [[CPUID]] and others).<ref name="Hennessy_2017"/>

This table shows opcodes of a simple 8-bit microprocessor, the [[Intel 8008]] from 1972.

Each opcode is 8 [[bit]]s long. Each is shown as a [[Binary number|binary]] pattern of ones and zeros in the '''Opcode''' column. Up to two additional fields may be embedded into the opcode. Some 3-bit fields are labeled DDD, SSS, CC, and ALU. The SSS (source) and DDD (destination) fields specify one of the eight possible 8008 [[Processor register|registers]] or memory: A, B, C, D, E, H, L, or M. CC specifies a condition that will activate certain JMP, CAL, and RET instructions. ALU specifies one of a possible eight [[arithmetic logic unit]] functions to be performed during an instruction, specifically, add, add with carry, subtract, subtract with borrow, logical AND, logical XOR, logical OR, and compare. The '''X''' in some fields means that either a 1 or 0 can be inserted with [[Don't-care term|no effect]].

The fixed ones and zeros are combined with the parameter fields to build the 8-bit opcode. Additionally, the full instruction might require one or two additional bytes of operands. These are shown in the second major column of the table, labeled '''Operands'''. If no operands are required, the column is filled with a dash (&mdash;).

Since the ones and zeros are difficult to remember, the '''Mnemonic''' column shows a short, easy to remember letter code that an [[assembly language]] programmer may use to invoke the required opcode.

The '''Description''' column shows the function performed by the microprocessor when it encounters a specific opcode.

{|class="wikitable" style="text-align:center"

!colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| Description

|-

! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3

|-

| 0 || 0 || 0 || 0 || 0 || 0 || 0 || X || &mdash; || &mdash; ||align=left| HLT ||align=left| Halt

|-

| 0 || 0 ||colspan=3|DDD || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| INr ||align=left| DDD ← DDD + 1 (except A and M)

|-

| 0 || 0 ||colspan=3|DDD || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| DCr ||align=left| DDD ← DDD - 1 (except A and M)

|-

| 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| RLC ||align=left| A_1-7 ← A_0-6; A₀ ← Cy ← A₇

|-

| 0 || 0 ||colspan=3|CC || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| Rcc (RET conditional) ||align=left| If cc true, P ← (stack)

|-

| 0 || 0 ||colspan=3|ALU || 1 || 0 || 0 || ''data'' || &mdash; ||align=left| ADI ACI SUI SBI NDI XRI ORI CPI ''data'' ||align=left| A ← A [ALU operation] data

|-

| 0 || 0 ||colspan=3|N || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| RST ''n'' ||align=left| (stack) ← P, P ← N x 8

|-

| 0 || 0 ||colspan=3|DDD || 1 || 1 || 0 || ''data'' || &mdash; ||align=left| LrI ''data'' (Load r with immediate data) ||align=left| DDD ← data

|-

| 0 || 0 || X || X || X || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RET ||align=left| P ← (stack)

|-

| 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| RRC ||align=left| A_0-6 ← A_1-7; A₇ ← Cy ← A₀

|-

| 0 || 0 || 0 || 1 || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| RAL ||align=left| A_1-7 ← A_0-6; Cy ← A₇; A₀ ← Cy

|-

| 0 || 0 || 0 || 1 || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| RAR ||align=left| A_0-6 ← A_1-7; Cy ← A₀; A₇ ← Cy

|-

| 0 || 1 ||colspan=3|CC || 0 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| Jcc ''add'' (JMP conditional)||align=left| If cc true, P ← add

|-

| 0 || 1 || 0 || 0 ||colspan=3|port || 1 || &mdash; || &mdash; ||align=left| INP ''port'' ||align=left| A ← Port (ports 0-7 only)

|-

| 0 || 1 ||colspan=5|port || 1 || &mdash; || &mdash; ||align=left| OUT ''port'' ||align=left| Port ← A (ports 8-31 only)

|-

| 0 || 1 ||colspan=3|CC || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| Ccc ''add'' (CAL conditional)|| align=left| If cc true, (stack) ← P, P ← add

|-

| 0 || 1 || X || X || X || 1 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| JMP ''add'' ||align=left| P ← add

|-

| 0 || 1 || X || X || X || 1 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| CAL ''add'' ||align=left| (stack) ← P, P ← add

|-

| 1 || 0 ||colspan=3|ALU ||colspan=3|SSS || &mdash; || &mdash; ||align=left| ADr ACr SUr SBr NDr XRr ORr CPr || align=left| A ← A [ALU operation] SSS

|-

| 1 || 1 ||colspan=3|DDD ||colspan=3|SSS || &mdash; || &mdash; ||align=left| Lds (Load d with s) ||align=left| DDD ← SSS

|-

| 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| HLT ||align=left| Halt

|-

! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || Description

|-

!colspan=13|

|-

!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU

|-

|colspan=5| A || 0 || 0 || 0 ||colspan=2|FC, C false ||align=left|ADr ADI (A ← A + arg)

|-

|colspan=5| B || 0 || 0 || 1||colspan=2|FZ, Z false||align=left|ACr ACI (A ← A + arg + Cy)

|-

|colspan=5| C || 0 || 1 || 0||colspan=2|FS, S false ||align=left|SUr SUI (A ← A - arg)

|-

|colspan=5| D || 0 || 1 || 1||colspan=2|FP, P odd ||align=left|SBr SBI (A ← A - arg - Cy)

|-

|colspan=5| E || 1 || 0 || 0||colspan=2|TC, C true ||align=left|NDr NDI (A ← A ∧ arg)

|-

|colspan=5| H || 1 || 0 || 1||colspan=2|TZ, Z true ||align=left|XRr XRI (A ← A ⊻ arg)

|-

|colspan=5| L || 1 || 1 || 0||colspan=2|TS, S true ||align=left|ORr ORI (A ← A ∨ arg)

|-

|colspan=5| M || 1 || 1 || 1||colspan=2|TP, P even ||align=left|CPr CPI (A - arg)

|-

!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU

|}

=={{Anchor|SIS}}Software instruction sets==

Opcodes can be found in so-called [[byte codebytecode]]s and other representations intended for aexecution by software interpreter rather than a hardware deviceinterpreters. These software-based instruction sets often employ slightly higher-level data types and operations than mostthose found in hardware counterparts,opcodes but are nevertheless constructed along similar lines. Examples include the byte code found in [[Java class file]]s, which are then interpreted by the [[Java virtual machine|Java Virtual Machine]] (JVM)s, the byte code used in [[GNU Emacs]] for compiled [[Lisp (programming language)|Lisp]] code, .and NET [[Common Intermediate Language]] (CIL), and many others.<ref name="bytecode"/>

==See also==