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== Features ==
*Dual memory controllers for Ivy Bridge-EP and Ivy Bridge-EX<ref name="anandtech-xeon-e5-2600-v2">{{cite web|date=September 17, 2013|title=Intel's Xeon E5-2600 V2: 12-core Ivy Bridge EP for Servers|url=http://www.anandtech.com/show/7285/intel-xeon-e5-2600-v2-12-core-ivy-bridge-ep|archive-url=https://web.archive.org/web/20130919233857/http://www.anandtech.com/show/7285/intel-xeon-e5-2600-v2-12-core-ivy-bridge-ep|url-status=dead|archive-date=September 19, 2013|access-date=January 21, 2014|publisher=AnandTech}}</ref>
* Up to 12 CPU cores and 30 MB of L3 cache for Ivy Bridge-EP<ref name="anandtech-xeon-e5-2600-v2" />
* Up to 15 CPU cores and 37.5 MB L3 cache for Ivy Bridge-EX<ref>{{cite web|title=Some details of Ivy Bridge-EX processors|url=http://www.cpu-world.com/news_2013/2013100101_Some_details_of_Ivy_Bridge-EX_processors.html|access-date=October 12, 2013|publisher=Cpu-world.com}}</ref> (released on February 18, 2014 as Xeon E7 v2<ref>{{cite web|author=Charlie Demerjian|title=Intel releases Ivy Bridge-EX now known as Xeon E7 v2|date=18 February 2014 |url=http://semiaccurate.com/2014/02/18/intel-releases-ivy-bridge-ex-now-known-xeon-e7-v2/|access-date=February 19, 2014|publisher=SemiAccurate}}</ref>)
* Thermal design power between 50 W and 155 W<ref>{{cite web|date=February 2, 2014|title=Intel Xeon E7 'Ivy Bridge-EX' Lineup Detailed – Xeon E7-8890 V2 'Ivy Town' Chip With 15 Cores and 37.5 MB LLC|url=http://wccftech.com/intel-xeon-e7-ivy-bridgeex-lineup-detailed-xeon-e78890-v2-ivy-town-chip-15-cores-375-mb-llc/|access-date=February 16, 2014|publisher=Wccftech.com}}</ref>
* Support for up to eight [[DIMM]]s of DDR3-1866 memory per socket, with reductions in memory speed depending on the number of DIMMs per [[Multi-channel memory architecture|channel]]<ref>{{cite web|author=Johan De Gelas|date=December 19, 2013|title=Server Buying Decisions: Memory|url=http://www.anandtech.com/show/7479/server-buying-decisions-memory/2|archive-url=https://web.archive.org/web/20131222023223/http://anandtech.com/show/7479/server-buying-decisions-memory/2|url-status=dead|archive-date=December 22, 2013|access-date=September 9, 2014|publisher=[[AnandTech]]}}</ref><ref>{{cite web|date=November 14, 2013|title=Fujitsu PRIMERGY Servers Memory Performance of Xeon E5-2600 v2 (Ivy Bridge-EP) based Systems|url=http://globalsp.ts.fujitsu.com/dmsp/Publications/public/wp-ivy-bridge-ep-memory-performance-ww-en.pdf|access-date=September 9, 2014|website=fujitsu.com|pages=4–5}}</ref><ref>{{cite web|author=Jason Fan|year=2013|title=The importance of proper memory configuration for optimal performance (Intel Reference – E5-2600 v2 DDR3 RDIMM Memory Speeds; Intel Reference – E5-2600 v2 DDR3 LRDIMM & ECC UDIMM Memory Speeds)|url=http://www.worldhostingdays.com/downloads/2013-china/mF1a.pdf|url-status=dead|archive-url=https://web.archive.org/web/20140910200016/http://www.worldhostingdays.com/downloads/2013-china/mF1a.pdf|archive-date=September 10, 2014|access-date=September 9, 2014|website=worldhostingdays.com|publisher=[[Kingston Technology]]|pages=7–8|df=dmy-all}}</ref>
* No integrated GPU
* Ivy Bridge-EP introduced new hardware support for interrupt virtualization, branded as [[APICv]].<ref>{{cite web|author=Khang Nguyen|date=December 17, 2013|title=APIC Virtualization Performance Testing and Iozone|url=https://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone|access-date=July 12, 2014|website=software.intel.com}}</ref><ref>{{cite web|date=March 14, 2014|title=Product Brief Intel Xeon Processor E5-4600 v2 Product Family|url=http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-e5-4600-v2-brief.pdf|access-date=July 12, 2014|publisher=Intel}}</ref>
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