Bus (computing): Difference between revisions

Revision as of 03:49, 14 November 2024

Latest revision as of 05:31, 6 August 2025

(30 intermediate revisions by 21 users not shown)

Line 1:

{{Short description|Data transfer channel betweenconnecting parts of a computer}}

{{About|buses in computer hardware|buses in software|Software bus}}

{{Use American English|date=March 2016}}

Line 6:

[[File:PCIExpress.jpg|250px|thumb|Four [[PCI Express]] bus card slots (from top to second from bottom: ×4, ×16, ×1 and ×16), compared to a 32-bit [[conventional PCI]] bus card slot (very bottom)]]

In [[computer architecture]], a '''bus''' (historically also called a '''data highway'''<ref name="Hollingdale_1958">{{cite conference |conference=Applications of Computers, University of Nottingham 15–19 September 1958 |title=Session 14. Data Processing |author-first=Stuart H. |author-last=Hollingdale |date=1958-09-19 |url=https://www.chilton-computing.org.uk/acl/literature/othermanuals/nottingham/p014.htm}}</ref> or '''databus''') is a communication system that transfers [[Data (computing)|data]] between components inside a [[computer]] or between computers.<ref>{{cite book |url=https://books.google.com/books?id=YVi8HVN-APwC&q=computer+buss+-sam&pg=PA27 |title=What Every Engineer Should Know about Data Communications |first=Carl |last=Clifton |publisher=CRC Press |date=September 19, 1986 |page=27 |isbn=9780824775667 |quote=The internal computer bus is a parallel transmission scheme; within the computer.... |url-status=live |archive-url=https://web.archive.org/web/20180117151300/https://books.google.com/books?id=YVi8HVN-APwC&lpg=PA27&dq=computer%20buss%20-sam&pg=PA27#v=onepage&q=computer%20buss%20-sam&f=false |archive-date=January 17, 2018}}</ref> It encompasses both [[Computer hardware|hardware]] (e.g., wires, [[optical fiber]]) and [[software]], including [[communication protocol]]s.<ref>{{cite web |url=https://www.pcmag.com/encyclopedia/term/39054/bus |title=bus Definition from PC Magazine Encyclopedia |publisher=pcmag.com |date=2014-05-29 |access-date=2014-06-21 |url-status=live |archive-url=https://web.archive.org/web/20150207204630/http://www.pcmag.com/encyclopedia/term/39054/bus |archive-date=2015-02-07}}</ref> At its core, a bus is a shared physical pathway, typically composed of wires, traces on a circuit board, or [[busbar]]s, that allows multiple devices to communicate. To prevent conflicts and ensure orderly data exchange, buses rely on a [[communication protocol]] to manage which device can transmit data at a given time.

In [[computer architecture]], a '''bus'''<ref>{{cite book

|url = https://books.google.com/books?id=YVi8HVN-APwC&q=computer+buss+-sam&pg=PA27

|title = What Every Engineer Should Know about Data Communications

|first = Carl

|last = Clifton

|publisher = CRC Press

|date = September 19, 1986

|page = 27

|isbn = 9780824775667

|quote = The internal computer bus is a parallel transmission scheme; within the computer....

|url-status = live

|archive-url = https://web.archive.org/web/20180117151300/https://books.google.com/books?id=YVi8HVN-APwC&lpg=PA27&dq=computer%20buss%20-sam&pg=PA27#v=onepage&q=computer%20buss%20-sam&f=false

|archive-date = January 17, 2018

}}</ref> (historically also called '''data highway'''<ref name="Hollingdale_1958"/> or '''databus''') is a communication system that transfers [[Data (computing)|data]] between components inside a [[computer]], or between computers. This expression covers all related [[Computer hardware|hardware]] components (wire, [[optical fiber]], etc.) and [[software]], including [[communication protocol]]s.<ref>{{cite web |url=https://www.pcmag.com/encyclopedia/term/39054/bus |title=bus Definition from PC Magazine Encyclopedia |publisher=pcmag.com |date=2014-05-29 |access-date=2014-06-21 |url-status=live |archive-url=https://web.archive.org/web/20150207204630/http://www.pcmag.com/encyclopedia/term/39054/bus |archive-date=2015-02-07 }}</ref>

Buses are categorized based on their role, such as [[system bus]]es (also known as internal buses, internal data buses, or memory buses) connecting the [[Central processing unit|CPU]] and [[Computer memory|memory]]. [[Expansion bus]]es, also called [[peripheral bus]]es, extend the system to connect additional devices, including [[peripheral]]s. Examples of widely used buses include [[PCI Express]] (PCIe) for high-speed internal connections and [[Universal Serial Bus]] (USB) for connecting external devices.

In most traditional [[computer architecture]]s, the CPU and main memory tend to be tightly coupled, with the internal bus connecting the two being known as the [[system bus]]. In systems that include a [[Cache (computing)|cache]], CPUs use high-performance system buses that operate at speeds greater than memory to communicate with memory. The internal bus (also known as the internal data bus, memory bus or [[system bus]]) connects internal components of a computer to the mother board. [[Local bus|Local buses]] connect the CPU and memory to the [[expansion bus]], which in turn connects the computer to peripherals. Bus systems such as the [[SATA]] ports in modern computers support multiple peripherals, allowing multiple hard drives to be connected without an [[expansion card]].

Modern buses utilize both [[parallel communication|parallel]] and [[serial communication]], employing advanced encoding methods to maximize speed and efficiency. Features such as [[direct memory access]] (DMA) further enhance performance by allowing data transfers directly between devices and memory without requiring CPU intervention.

In systems that have a similar architecture to [[Distributed computing|multicomputers]], but which communicate by buses instead of networks, the system bus is known as a [[front-side bus]]. In such systems, the expansion bus may not share any architecture with their host CPUs, instead supporting many different CPUs, as is the case with [[Peripheral Component Interconnect|PCI]]. While the term "[[peripheral bus]]" is sometimes used to refer to all other buses apart from the system bus, the "expansion bus" has also been used to describe a third category of buses separate from the peripheral bus, which includes bus systems like PCI.

Early computer buses were parallel electrical wires with multiple hardware connections, but the term is now used for any physical arrangement that provides the same logical function as a parallel [[busbar|electrical busbar]]. Modern computer buses can use both [[parallel communication|parallel]] and [[Serial communication|bit serial]] connections, and can be wired in either a [[multidrop]] (electrical parallel) or [[Daisy chain (electrical engineering)|daisy chain]] topology, or connected by switched hubs. Many modern CPUs also feature a second set of pins similar to those for communicating with memory—but able to operate with different speeds and protocols—to ensure that peripherals do not slow overall system performance. CPUs can also feature smart [[Controller (computing)|controllers]] to place the data directly in memory, a concept known as [[direct memory access]]. Low-performance bus systems have also been developed, such as the [[Universal Serial Bus]] (USB).

Given technological changes, the classical terms "system", "expansion" and "peripheral" no longer have the same connotations. Other common categorization systems are based on the bus's primary role, connecting devices internally or externally. However, many common modern bus systems can be used for both. [[SATA]] and the associated [[eSATA]] are one example of a system that would formerly be described as internal, while certain automotive applications use the primarily external [[IEEE 1394]] in a fashion more similar to a system bus. Other examples, like [[InfiniBand]] and [[I²C]] were designed from the start to be used both internally and externally.

==Address bus==

{{Unreferenced section|date=June 2023}}

An ''address bus'' is a bus that is used to specify a [[physical address]]. When a [[central processing unit|processor]] or [[direct memory access|DMA]]-enabled device needs to read or write to a memory ___location, it specifies that memory ___location on the address bus (the value to be read or written is sent on the data bus). The width of the address bus determines the amount of memory a system can address. For example, a system with a ''32-bit'' address bus can address ''2³²'' (4,294,967,296) memory locations. If each memory ___location holds one byte, the addressable memory space is about {{val|4&nbsp;|ul=GB}}.

=== Address multiplexing ===

Line 41 ⟶ 24:

Accessing an individual byte frequently requires reading or writing the full bus width (a [[Word (data type)|word]]) at once. In these instances the least significant bits of the address bus may not even be implemented - it is instead the responsibility of the controlling device to isolate the individual byte required from the complete word transmitted. This is the case, for instance, with the [[VESA Local Bus]] which lacks the two least significant bits, limiting this bus to [[Data structure alignment|aligned]] 32-bit transfers.

Historically, there were also some examples of computers whichthat were only able to address words -- {{snd}}[[word machine]]s.

==Memory bus==

{{Unreferenced section|date=June 2023}}

The ''memory bus'' is the bus whichthat connects the [[main memory]] to the [[memory controller]] in [[computer systems]]. Originally, general-purpose buses like [[VMEbus]] and the [[S-100 bus]] were used, but to reduce [[latency (engineering)|latency]], modern memory buses are designed to connect directly to DRAM chips, and thus are designeddefined by chip standards bodies such as [[JEDEC]]. Examples are the various generations of [[SDRAM]], and serial point-to-point buses like [[SLDRAM]] and [[RDRAM]]. An exception is the [[Fully Buffered DIMM]] which, despite being carefully designed to minimize the effect, has been criticized for its higher latency.

==Implementation details==

Buses can be [[parallel bus]]es, which carry [[computerdata word|data words]]s in parallel on multiple wires, or [[serial bus]]es, which carry data in bit-serial form. The addition of extra power and control connections, [[differential signaling|differential driver]]s, and data connections in each direction usually means that most serial buses have more conductors than the minimum of one used in [[1-Wire]] and [[UNI/O]]. As data rates increase, the problems of [[timing skew]], power consumption, electromagnetic interference and [[crosstalk]] across parallel buses become more and more difficult to circumvent. One partial solution to this problem has been to [[double pump]] the bus. Often, a serial bus can be operated at higher overall data rates than a parallel bus, despite having fewer electrical connections, because a serial bus inherently has no timing skew or crosstalk. [[USB]], [[FireWire]], and [[Serial ATA]] are examples of this. [[Multidrop]] connections do not work well for fast serial buses, so most modern serial buses use [[Daisy chain (information technology)#Computer hardware|daisy-chain]] or hub designs.

The transition from parallel to serial buses was allowed by [[Moore's law]] which allowed for the incorporation of [[SerDes|serializer/deserializers]] in integrated circuits which are used in computers.<ref>{{cite book | url=https://books.google.com/books?id=aUCgNOpyUbgC&dq=parallel++serial++serdes+moore%27s+law&pg=PA275 | isbn=978-1-4020-7496-7 | title=The Boundary — Scan Handbook | date=30 June 2003 | publisher=Springer }}</ref>

[[computer network|Network]] connections such as [[Ethernet]] are not generally regarded as buses, although the difference is largely conceptual rather than practical. An attribute generally used to characterize a bus is that power is provided by the bus for the connected hardware. This emphasizes the [[busbar]] origins of bus architecture as supplying switched or distributed power. This excludes, as buses, schemes such as serial [[RS-232]], parallel [[Centronics]], [[IEEE 1284]] interfaces and Ethernet, since these devices also needed separate power supplies. [[Universal Serial Bus]] devices may use the bus supplied power, but often use a separate power source. This distinction is exemplified by a [[Plain old telephone service|telephone]] system with a connected [[modem]], where the [[RJ11]] connection and associated modulated signalling scheme is not considered a bus, and is analogous to an [[Ethernet]] connection. A phone line connection scheme is not considered to be a bus with respect to signals, but the [[telephone exchange|Central Office]] uses buses with [[cross-bar switch]]es for connections between phones.

However, this distinction{{mdashb}}that power is provided by the bus{{mdashb}}is not the case in many [[avionics|avionic systems]], where data connections such as [[ARINC 429]], [[ARINC 629]], [[MIL-STD-1553B]] (STANAG 3838), and EFABus ([[STANAG 3910]]) are commonly referred to as “data''data buses”buses'' or, sometimes, "''databuses"''. Such [[avionics#Aircraft networks|avionic data buses]] are usually characterized by having several equipments or [[Line-replaceable unit|Line Replaceable Items/Units]] (LRI/LRUs) connected to a common, shared [[Media (communication)|media]]. They may, as with ARINC 429, be [[Simplex communication|simplex]], i.e. have a single source LRI/LRU or, as with ARINC 629, MIL-STD-1553B, and STANAG 3910, be [[Duplex (telecommunications)|duplex]], allow all the connected LRI/LRUs to act, at different times ([[half duplex]]), as transmitters and receivers of data.<ref name = "ASSC 2003">Avionic Systems Standardisation Committee, ''Guide to Digital Interface Standards For Military Avionic Applications'', ASSC/110/6/2, Issue 2, September 2003</ref>

The frequency or the speed of a bus is measured in Hz such as MHz and determines how many clock cycles there are per second; there can be one or more data transfers per clock cycle. If there is a single transfer per clock cycle it is known as [[Single Data Rate]] (SDR), and if there are two transfers per clock cycle it is known as [[Double Data Rate]] (DDR) although the use of signalling other than SDR is uncommon outside of RAM. An example of this is PCIe which uses SDR.<ref>{{cite book | url=https://books.google.com/books?id=M_TKDwAAQBAJ&dq=pcie+rate&pg=PA155 | isbn=978-0-7384-5812-0 | title=IBM z15 (8561) Technical Guide | date=13 July 2022 | publisher=IBM Redbooks }}</ref> Within each data transfer there can be multiple bits of data. This is described as the width of a bus which is the number of bits the bus can transfer per clock cycle and can be synonymous with the number of physical electrical conductors the bus has if each conductor transfers one bit at a time.<ref>{{cite book | url=https://books.google.com/books?id=hDwDEAAAQBAJ&dq=bus+width&pg=PA54 | isbn=978-1-000-11716-5 | title=Foundations of Computer Technology | date=25 October 2020 | publisher=CRC Press }}</ref><ref>{{cite book | url=https://books.google.com/books?id=j0wsBgAAQBAJ&dq=computer+bus+frequency&pg=PA39 | title=PC Systems, Installation and Maintenance | isbn=978-1-136-37442-5 | last1=Beales | first1=R. P. | date=11 August 2006 | publisher=Routledge }}</ref><ref>{{cite web | url=https://computer.howstuffworks.com/motherboard4.htm#:~:text=Bus%20speed%20usually%20refers%20to,dramatically%20affect%20a%20computer%27s%20performance | title=How Motherboards Work | date=20 July 2005 }}</ref> The data rate in bits per second can be obtained by multiplying the number of bits per clock cycle times the frequency times the number of transfers per clock cycle.<ref>{{cite book | url=https://books.google.com/books?id=6FnMBQAAQBAJ&q=Data+rate&pg=PA92 | title=Computer Busses | isbn=978-1-4200-4168-2 | last1=Buchanan | first1=Bill | date=25 April 2000 | publisher=CRC Press }}</ref><ref>{{cite book | url=https://books.google.com/books?id=vpnJDwAAQBAJ&q=Width | title=The Computer Engineering Handbook | isbn=978-1-4398-3316-2 | last1=Oklobdzija | first1=Vojin G. | date=5 July 2019 | publisher=CRC Press }}</ref> Alternatively a bus such as [[PCIe]] can use modulation or encoding such as [[PAM4]]<ref>{{Cite web |last=Robinson |first=Dan |date=2022-01-12 |title=Final PCIe 6.0 specs unleashed: 64 GTps link speed incoming... with products to follow in 2023 |url=https://www.theregister.com/2022/01/12/final_pcie_60_specs_released/ |website=www.theregister.com}}</ref><ref>{{cite web | url=https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | archive-url=https://web.archive.org/web/20240404125350/https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | url-status=dead | archive-date=4 April 2024 | title=PCIe 7.0 Draft 0.5 Spec Available: 512 GB/S over PCIe x16 on Track for 2025 }}</ref><ref>{{cite web | url=https://arstechnica.com/gadgets/2022/01/pci-express-6-0-spec-is-finalized-doubling-bandwidth-for-ssds-gpus-and-more/ | title=PCIe 5.0 is just beginning to come to new PCS, but version 6.0 is already here | date=12 January 2022 }}</ref> which groups 2 bits into symbols which are then transferred instead of the bits themselves, and allows for an increase in data transfer speed without increasing the frequency of the bus. The effective or real data transfer speed/rate may be lower due to the use of encoding that also allows for error correction such as 128/130b (b for bit) encoding.<ref>{{cite web | url=https://www.xda-developers.com/pcie-6/ | title=PCIe 6.0: Everything you need to know about the upcoming standard | date=30 June 2024 }}</ref><ref>{{cite web | url=https://semiengineering.com/knowledge_centers/communications-io/off-chip-communications/pam-4-signaling/ | title=PAM-4 Signaling }}</ref><ref>{{cite book | url=https://books.google.com/books?id=M_TKDwAAQBAJ&dq=pcie+rate&pg=PA155 | isbn=978-0-7384-5812-0 | title=IBM z15 (8561) Technical Guide | date=13 July 2022 | publisher=IBM Redbooks }}</ref> The data transfer speed is also known as the bandwidth.<ref>{{cite book | url=https://books.google.com/books?id=eV1_LjW3pTkC&dq=agp+2133&pg=PA304 | isbn=978-0-7897-2745-9 | title=Upgrading and Repairing PCS | date=2003 | publisher=Que }}</ref><ref>{{cite web | url=https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | archive-url=https://web.archive.org/web/20240404125350/https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | url-status=dead | archive-date=4 April 2024 | title=PCIe 7.0 Draft 0.5 Spec Available: 512 GB/S over PCIe x16 on Track for 2025 }}</ref>

=== Bus multiplexing ===

Line 75 ⟶ 58:

One common multiplexing scheme, [[#Address multiplexing|address multiplexing]], has already been mentioned.

Another multiplexing scheme re-uses the address bus pins as the data bus pins,<ref name="typewriter" /> an approach used by [[conventional PCI]] and the [[8086]].

The various "''serial buses"'' can be seen as the ultimate limit of multiplexing, sending each of the address bits and each of the data bits, one at a time, through a single pin (or a single differential pair).

==History==

Over time, several groups of people worked on various computer bus standards, including the IEEE Bus Architecture Standards Committee (BASC), the IEEE "Superbus" study group, the open microprocessor initiative (OMI), the open microsystems initiative (OMI), the "Gang of Nine" that developed [[Extended Industry Standard Architecture|EISA]], etc.{{Citation needed|date=January 2015}}

===First generation===

Early [[computer]] buses were bundles of wire that attached [[computer memory]] and peripherals. Anecdotally termed the "''digit trunk''" in the early Australian [[CSIRAC]] computer,<ref>{{cite book|last1=McCann|first1=Doug|last2=Thorne|first2=Peter|title=The Last of The First, CSIRAC: Australias First Computer|pages=8–11, 13, 91|publisher=University of Melbourne Computing Science|year=2000|url=https://cis.unimelb.edu.au/about/csirac/last-of-the-first|isbn=0-7340-2024-4}}</ref> they were named after electrical power buses, or [[busbar]]s. Almost always, there was one bus for memory, and one or more separate buses for peripherals. These were accessed by separate instructions, with completely different timings and protocols.

One of the first complications was the use of [[interrupt]]s. Early computer programs performed [[I/O]] by [[Busy waiting|waiting in a loop]] for the peripheral to become ready. This was a waste of time for programs that had other tasks to do. Also, if the program attempted to perform those other tasks, it might take too long for the program to check again, resulting in loss of data. Engineers thus arranged for the peripherals to interrupt the CPU. The interrupts had to be prioritized, because the CPU can only execute code for one peripheral at a time, and some devices are more time-critical than others.

Line 97 ⟶ 80:

Early [[microcomputer]] bus systems were essentially a passive [[backplane]] connected directly or through buffer amplifiers to the pins of the [[CPU]]. Memory and other devices would be added to the bus using the same address and data pins as the CPU itself used, connected in parallel. Communication was controlled by the CPU, which read and wrote data from the devices as if they are blocks of memory, using the same instructions, all timed by a central clock controlling the speed of the CPU. Still, devices [[interrupt]]ed the CPU by signaling on separate CPU pins.

For instance, a [[disk drive]] controller would signal the CPU that new data was ready to be read, at which point the CPU would move the data by reading the "memory ___location" that corresponded to the disk drive. Almost all early microcomputers were built in this fashion, starting with the [[S-100 bus]] in the [[Altair 8800]] computer system.

In some instances, most notably in the [[IBM PC]], although similar physical architecture can be employed, instructions to access peripherals (<code>in</code> and <code>out</code>) and memory (<code>mov</code> and others) have not been made uniform at all, and still generate distinct CPU signals, that could be used to implement a separate I/O bus.

Line 109 ⟶ 92:

===Second generation===

{{Unreferenced section|date=June 2023}}

"Second -generation" bus systems like [[NuBus]] addressed some of these problems. They typically separated the computer into two "worlds"[[address space]]s, the CPU and memory on one side, and the various peripheral devices on the other. A ''bus controller'' accepted data from the CPU side to be moved to the peripherals side, thus shifting the communications protocol burden from the CPU itself. This allowed the CPU and memory side to evolve separately from the deviceperipheral bus, or just "bus". Devices on the bus could talk to each other with no CPU intervention. This led to much better "real world" performance, but also required the cards to be much more complex. These buses also often addressed speed issues by being "bigger" in terms of the size of the data path, moving from 8-bit [[parallel bus]]es in the first generation, to 16 or 32-bit in the second, as well as adding software setup (nowlater standardisedstandardized as [[Plug-n-play]]) to supplant or replace the jumpers.

However, these newer systems shared one quality with their earlier cousins, in that everyone on the bus had to talk at the same speed. While the CPU was now isolated and could increase speed, CPUs and memory continued to increase in speed much faster than the buses they talked to. The result was that the bus speeds were now much slower than what a modern system needed, and the machines were left starved for data. A particularly common example of this problem was that [[video card]]s quickly outran even the newer bus systems like [[PCI Local Bus|PCI]], and computers began to include [[Accelerated Graphics Port|AGP]] just to drive the video card. By 2004 AGP was outgrown again by high-end video cards and other peripherals and has been replaced by the new [[PCI Express]] bus.

Line 118 ⟶ 101:

{{See also|Bus network}}

"Third -generation" buses have been emerging into the market since about 2001, including [[HyperTransport]] and [[InfiniBand]]. They also tend to be very flexible in terms of their physical connections, allowing them to be used both as internal buses, as well as connecting different machines together. This can lead to complex problems when trying to service different requests, so much of the work on these systems concerns software design, as opposed to the hardware itself. In general, these third -generation buses tend to look more like a [[Computer network|network]] than the original concept of a bus, with a higher protocol overhead needed than early systems, while also allowing multiple devices to use the bus at once.

Buses such as [[Wishbone (computer bus)|Wishbone]] have been developed by the [[open source hardware]] movement in an attempt to further remove legal and patent constraints from computer design.

Line 172 ⟶ 155:

* [[UNI/O]]

* [[SMBus]]

* [[Advanced eXtensible Interface]]

* [[M-PHY]]

{{Div col end}}

Line 184 ⟶ 169:

===Serial===

Many [[field bus]]es are serial data buses (not to be confused with the parallel "data bus" section of a [[system bus]] or [[expansion card]]), several of which use the [[RS-485]] electrical characteristics and then specify their own protocol and connector:

* [[CAN bus]] ("Controller Area Network")

* [[Modbus]]

Line 222 ⟶ 207:

* [[Bus mastering]]

* [[Communication endpoint]]

* [[Computer port (hardware)]]

* [[Control bus]]

* [[Crossbar switch]]

Line 237 ⟶ 223:

==References==

{{Reflist|refs=

<ref name="Hollingdale_1958">{{cite conference |conference=Applications of Computers, University of Nottingham 15–19 September 1958 |title=Session 14. Data Processing |author-first=Stuart H. |author-last=Hollingdale |date=1958-09-19 |url=https://www.chilton-computing.org.uk/acl/literature/othermanuals/nottingham/p014.htm}}</ref>

}}