Microcode: Difference between revisions

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{{Program execution}}

In [[processor design]], '''microcode''' serves as an intermediary layer situated between the [[central processing unit]] (CPU) hardware and the programmer-visible [[instruction set architecture]] of a computer, also known as its [[machine code]].<ref name="Kent2813">{{cite book |last1=Kent |first1=Allen |url=https://books.google.com/books?id=EjWV8J8CQEYC |title=Encyclopedia of Computer Science and Technology: Volume 28 - Supplement 13 |last2=Williams |first2=James G. |date=April 5, 1993 |publisher=Marcel Dekker, Inc |isbn=0-8247-2281-7 |___location=New York |page=34 |access-date=Jan 17, 2016 |archive-url=https://web.archive.org/web/20161120161636/https://books.google.com/books?id=EjWV8J8CQEYC |archive-date=November 20, 2016 |url-status=live}}</ref>{{Page needed|date=July 2022}} It consists of a set of hardware-level instructions that implement the higher-level [[machine code]] instructions or control internal [[finite-state machine]] sequencing in many [[digital processing]] components. While microcode is utilized in [[Intel]] and [[AMD]] general-purpose CPUs in contemporary desktops and laptops, it functions only as a fallback path for scenarios that the faster [[hardwired control unit]] is unable to manage.<ref name="FogMicro">{{cite report |url=https://www.agner.org/optimize/microarchitecture.pdf |title=The microarchitecture of Intel, AMD and VIA CPUs |last1=Fog |first1=Agner |date=2017-05-02 |publisher=Technical University of Denmark |access-date=2024-08-21 |archive-url= https://web.archive.org/web/20170328065929/https://agner.org/optimize/microarchitecture.pdf |archive-date=2017-03-28 |url-status=live}}</ref>

Housed in special high-speed memory, microcode translates machine instructions, [[state machine]] data, or other input into sequences of detailed circuit-level operations. It separates the machine instructions from the underlying [[electronics]], thereby enabling greater flexibility in designing and altering instructions. Moreover, it facilitates the construction of complex multi-step instructions, while simultaneously reducing the complexity of computer circuits. The act of writing microcode is often referred to as ''microprogramming'', and the microcode in a specific processor implementation is sometimes termed a ''microprogram''.

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To properly perform an instruction, the various circuits have to be activated in order. For instance, it is not possible to add two numbers if they have not yet been loaded from memory. In [[RISC]] designs, the proper ordering of these instructions is largely up to the programmer, or at least to the [[compiler]] of the [[programming language]] they are using. So to add two numbers, for instance, the compiler may output instructions to load one of the values into one register, the second into another, call the addition function in the ALU, and then write the result back out to memory.<ref name=CPU/>

As the sequence of instructions needed to complete this higher-level concept, "add these two numbers in memory", may require multiple instructions, this can represent a performance bottleneck if those instructions are stored in [[main memory]]. Reading those instructions one by one is taking uptakes time that could be used to read and write the actual data. For this reason, it is common for non-RISC designs to have many different instructions that differ largely on where they store data. For instance, the [[MOS 6502]] has eight variations of the addition instruction, {{code|ADC}}, which differ only in where they look to find the two operands.<ref>{{cite web |url=http://www.6502.org/tutorials/6502opcodes.html |title= NMOS 6502 Opcodes |first= John |last=Pickens |website=6502.org}}</ref>

Using the variation of the instruction, or "[[opcode]]", that most closely matches the ultimate operation can reduce the number of instructions to one, saving memory used by the program code and improving performance by leaving the [[data bus]] open for other operations. Internally, however, these instructions are not separate operations, but sequences of the operations the units actually perform. Converting a single instruction read from memory into the sequence of internal actions is the duty of the [[control unit]], another unit within the processor.<ref name=microcode>{{cite web |url=http://www.righto.com/2022/11/how-8086-processors-microcode-engine.html#:~:text=In%201951%2C%20Maurice%20Wilkes%20came,memory%20called%20a%20control%20store. |title=How the 8086 processor's microcode engine works |website=Ken Shirriff's blog |first=Ken |last=Shirriff}}</ref>

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==History==

===Early examples===

The ACE computer, designed by [[Alan Turing]] in 1946, used microprogramming.<ref>{{cite book | title=Modern Mathematics | date=2006 | publisher=Infobase | isbn=978-0-7910-9720-5 | url=https://books.google.com/books?id=5LMVSFNhFI0C&dq=ace+microprogramming&pg=PA121 }}</ref>

In 1947, the design of the [[Whirlwind (computer)|MIT Whirlwind]] introduced the concept of a control store as a way to simplify computer design and move beyond ''[[ad hoc]]'' methods. The control store is a [[diode matrix]]: a two-dimensional lattice, where one dimension accepts "control time pulses" from the CPU's internal clock, and the other connects to control signals on gates and other circuits. A "pulse distributor" takes the pulses generated by the [[CPU clock]] and breaks them up into eight separate time pulses, each of which activates a different row of the lattice. When the row is activated, it activates the control signals connected to it.<ref>{{Cite tech report |last1=Everett |first1=R.R. |last2=Swain |first2=F.E. |year=1947 |title=Whirlwind I Computer Block Diagrams |publisher=MIT Servomechanisms Laboratory |id=R-127 |url=http://www.cryptosmith.com/wp-content/uploads/2009/05/whirlwindr-127.pdf |access-date=June 21, 2006 |url-status=dead |archive-url=https://web.archive.org/web/20120617112919/http://www.cryptosmith.com/wp-content/uploads/2009/05/whirlwindr-127.pdf |archive-date=June 17, 2012}}</ref>

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===The 360===

{{main|System/360}}

Microcode remained relatively rare in computer design as the cost of the ROM needed to store the code was not significantly different thanfrom usingthe acost of custom control storelogic. This changed through the early 1960s with the introduction of mass-produced [[core memory]] and [[core rope]], which was far less expensive than dedicated logic based on diode arrays or similar solutions. The first to take real advantage of this was [[IBM]] in their 1964 [[System/360]] series. This allowed the machines to have a very complex instruction set, including operations that matched high-level language constructs like formatting binary values as decimal strings, storingencoding the complex series of instructionsinternal steps needed for this task in low cost memory.<ref name=IBM>{{cite web |url=https://www.righto.com/2022/01/ibm360model50.html |title=Simulating the IBM 360/50 mainframe from its microcode |website=Ken Shirriff's blog |first=Ken |last=Shirriff}}</ref>

But the real value in the 360 line was that one could build a series of machines that were completely different internally, yet run the same ISA. For a low-end machine, one might use an 8-bit ALU that requires multiple cycles to complete a single 32-bit addition, while a higher end machine might have a full 32-bit ALU that performs the same addition in a single cycle. These differences could be implemented in control logic, but the cost of implementing a completely different decoder for each machine would be prohibitive. Using microcode meant all that changed was the code in the ROM. For instance, one machine might include a [[floating point unit]] and thus its microcode for multiplying two numbers might be only a few lines line, whereas on the same machine without the FPU this would be a program that did the same using multiple additions, and all that changed was the ROM.<ref name=IBM/>

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The same basic evolution occurred with [[microprocessor]]s as well. Early designs were extremely simple, and even the more powerful 8-bit designs of the mid-1970s like the [[Zilog Z80]] had instruction sets that were simple enough to be implemented in dedicated logic. By this time, the control logic could be patterned into the same die as the CPU, making the difference in cost between ROM and logic less of an issue. However, it was not long before these companies were also facing the problem of introducing higher-performance designs but still wanting to offer [[backward compatibility]]. Among early examples of microcode in micros was the [[Intel 8086]].<ref name=microcode/>

Among the ultimate implementations of microcode in microprocessors is the [[Motorola 68000]]. This offered a highly [[orthogonal instruction set]] with a wide variety of [[addressing mode]]s, all implemented in microcode. This did not come without cost, according to early articles, about 20% of the chip's surface area (and thus cost) is the microcode system<ref>{{cite magazine |magazine=Byte |date= April 1983 |title=Design Philosophy Behind Motorola's MC68000 |first= Thomas |last= Starnes |url=http://www.easy68k.com/paulrsm/doc/dpbm68k1.htm}}</ref> and {{cn|reason=later estimates suggest approximately 23,000|date=December 2024}} of the systems 68,000 transistors were part of the microcode system.

===RISC enters===

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The result of this discovery was what is today known as the [[RISC]] concept. The complex microcode engine and its associated ROM is reduced or eliminated completely, and those circuits instead dedicated to things like additional registers or a wider ALU, which increases the performance of every program. When complex sequences of instructions are needed, this is left to the compiler, which is the entire purpose of using a compiler in the first place. The basic concept was soon picked up by university researchers in California, where simulations suggested such designs would trivially outperform even the fastest conventional designs. It was one such project, at the [[University of California, Berkeley]], that introduced the term RISC.

The industry responded to the concept of RISC with both confusion and hostility, including a famous dismissive article by the VAX team at Digital.<ref name=comments>{{cite journal |url=https://dl.acm.org/doi/pdf/10.1145/641914.641918 |title=Comments on "The Case for the Reduced Instruction Set Computer," by Patterson and Ditzel|first1=Douglas |last1=Clark |first2=William |last2=Strecker |date=September 1980 |journal= ACM SIGARCH Computer Architecture News|volume=8 |issue=6 |pages=34–38 |doi=10.1145/641914.641918 |s2cid=14939489 |url-access=subscription }}</ref> A major point of contention was that implementing the instructions outside of the processor meant it would spend much more time reading those instructions from memory, thereby slowing overall performance no matter how fast the CPU itself ran.<ref name=comments/> Proponents pointed out that simulations clearly showed the number of instructions was not much greater, especially when considering compiled code.<ref name=risc/>

The debate raged until the first commercial RISC designs emerged in the second half of the 1980s, which easily outperformed the most complex designs from other companies. By the late 1980s it was over; even DEC was abandoning microcode for their [[DEC Alpha]] designs, and CISC processors switched to using hardwired circuitry, rather than microcode, to perform many functions. For example, the [[Intel 80486]] uses hardwired circuitry to fetch and decode instructions, using microcode only to execute instructions; register-register move and arithmetic instructions required only one microinstruction, allowing them to be completed in one clock cycle.<ref>{{cite conference|url=https://ieeexplore.ieee.org/document/63682|title=The execution pipeline of the Intel i486 CPU|book-title= Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage|publisher=[[IEEE]]|isbn=0-8186-2028-5|___location=San Francisco, CA|doi=10.1109/CMPCON.1990.63682}}</ref> The [[Pentium Pro]]'s fetch and decode hardware fetches instructions and decodes them into series of micro-operations that are passed on to the execution unit, which schedules and executes the micro-operations, possibly doing so [[out-of-order execution|out-of-order]]. Complex instructions are implemented by microcode that consists of predefined sequences of micro-operations.<ref>{{cite web|url=http://stffrdhrn.github.io/content/2019/Intel_PentiumPro.pdf|title=Pentium Pro Processor At 150, 166, 180, and 200 MHz|publisher=[[Intel]]|date=November 1995|type=Datasheet}}</ref>

Some processor designs use machine code that runs in a special mode, with special instructions, available only in that mode, that have access to processor-dependent hardware, to implement some low-level features of the instruction set. The DEC Alpha, a pure RISC design, used [[PALcode]] to implement features such as [[translation lookaside buffer]] (TLB) miss handling and interrupt handling,<ref name="axp-architecture-manual">{{cite book|url=http://bitsavers.org/pdf/dec/alpha/Sites_AlphaAXPArchitectureReferenceManual_2ed_1995.pdf|title=Alpha AXP Architecture Reference Manual|edition=Second|chapter=Part I / Common Architecture, Chapter 6 Common PALcode Architecture|publisher=[[Digital Press]]|date=1995|isbn=1-55558-145-5}}</ref> as well as providing, for Alpha-based systems running [[OpenVMS]], instructions requiring interlocked memory access that are similar to instructions provided by the [[VAX]] architecture.<ref name="axp-architecture-manual" /> CMOS [[IBM System/390]] CPUs, starting with the G4 processor, and [[z/Architecture]] CPUs use [[millicode]] to implement some instructions.<ref>{{cite journal|last=Rogers|first=Bob|title=The What and Why of zEnterprise Millicode|journal=IBM Systems Magazine|date=Sep–Oct 2012|url=http://www.ibmsystemsmag.com/mainframe/administrator/performance/millicode_rogers/|archive-url=https://web.archive.org/web/20121009085728/http://www.ibmsystemsmag.com/mainframe/administrator/performance/millicode_rogers/|archive-date=October 9, 2012|url-status=dead}}</ref>

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* [[Microdata Corporation|Microdata]] produced computers in which the microcode is accessible to the user; this allows the creation of custom assembler level instructions. Microdata's [[Pick operating system|Reality]] operating system design makes extensive use of this capability.

* The [[Xerox Alto#Architecture|Xerox Alto]] workstation used a microcoded design but, unlike many computers, the microcode engine is not hidden from the programmer in a layered design. Applications take advantage of this to accelerate performance.

* The [[IBM System/38]] is described as having both [[IBM System/38#Microcode|horizontal and vertical microcode]].<ref>{{cite journal|url=https://www.computer.org/csdl/magazine/co/1981/09/01667517/13rRUwciPii|title=Design of a Small Business Data Processing System|first=Frank|last=Soltis|journal=[[IEEE Computer]]|date=September 1981|volume=14|pages=77–93|doi=10.1109/C-M.1981.220610|s2cid=398484|url-access=subscription}}</ref> In practice, the processor implements an instruction set architecture named the ''Internal Microprogrammed Interface'' (IMPI) using a horizontal microcode format. The so-called vertical microcode layer implements the System/38's hardware-independent [[IBM System/38#Machine Interface|Machine Interface]] (MI) instruction set by translating MI code to IMPI code and executing it. Prior to the introduction of the [[IBM RS64]] processor line, early [[IBM AS/400]] systems used the same architecture.<ref name="inside-as400">{{cite book|title=Inside the AS/400, Second Edition|url=https://books.google.com/books?id=5DoPAAAACAAJ|isbn=978-1882419661|author=Frank G. Soltis|year=1997|publisher=Duke Press}}</ref>

* The [[Nintendo 64]]'s [[Reality Coprocessor]] (RCP), which serves as the console's [[graphics processing unit]] and audio processor, utilizes microcode; it is possible to implement new effects or tweak the processor to achieve the desired output. Some notable examples of custom RCP microcode include the high-resolution graphics, particle engines, and unlimited draw distances found in [[Factor 5]]'s ''[[Indiana Jones and the Infernal Machine]]'', ''[[Star Wars: Rogue Squadron]]'', and ''[[Star Wars: Battle for Naboo]]'';<ref name="Interview: Battling the N64 (Naboo)">{{cite web |url=http://ign64.ign.com/articles/087/087646p1.html |title=Interview: Battling the N64 (Naboo) |publisher=IGN64 |date=November 10, 2000 |access-date=March 27, 2008 |url-status=live |archive-url=https://web.archive.org/web/20070913180626/http://ign64.ign.com/articles/087/087646p1.html |archive-date=September 13, 2007}}</ref><ref name="Indiana Jones and the Infernal Machine">{{cite web |title=Indiana Jones and the Infernal Machine |website=IGN |url=http://www.ign.com/articles/2000/12/13/indiana-jones-and-the-infernal-machine-2 |date=December 12, 2000 |access-date=September 24, 2013 |url-status=live |archive-url=https://web.archive.org/web/20130927083807/http://www.ign.com/articles/2000/12/13/indiana-jones-and-the-infernal-machine-2 |archive-date=September 27, 2013}}</ref> and the [[full motion video]] playback found in [[Rockstar San Diego|Angel Studios]]' ''[[Resident Evil 2]]''.<ref name="Postmortem RE2 N64">{{cite news |last=Meynink |first=Todd |date=July 28, 2000 |url=http://www.gamasutra.com/view/feature/3148/postmortem_angel_studios_.php |title=Postmortem: Angel Studios' Resident Evil 2 (N64 Version) |work=[[Gamasutra]] |publisher=[[United Business Media|United Business Media LLC]] |access-date=October 18, 2010 |url-status=livedead |archive-url=https://web.archive.org/web/20121021070818/http://www.gamasutra.com/view/feature/3148/postmortem_angel_studios_.php |archive-date=October 21, 2012}}</ref>

{{Further|topic=Nintendo 64 microcode|Nintendo 64 programming characteristics|Nintendo 64 Game Pak}}

* The VU0 and VU1 vector units in the [[Sony]] [[PlayStation 2]] are microprogrammable; in fact, VU1 is only accessible via microcode for the first several generations of the SDK.

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Starting with the [[Pentium Pro]] in 1995, several [[x86]] CPUs have writable [[Intel Microcode]].<ref name="Stiller_1996">{{cite journal |last1=Stiller |first1=Andreas |last2=Paul |first2=Matthias R.<!-- info contributor on processor internals --> |date=1996-05-12 |title=Prozessorgeflüster |series=Trends & News |language=de |journal=[[c't|c't – magazin für computertechnik]] |publisher=[[Heise Verlag]] |url=https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html |access-date=2017-08-28 |url-status=live |archive-url=https://web.archive.org/web/20170828172141/https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html |archive-date=2017-08-28}}</ref><ref>{{cite book |url=http://www.intel.com/Assets/PDF/manual/253668.pdf |title=Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, Part 1 |chapter=9.11: Microcode update facilities |publisher=[[Intel]] |date=September 2016}}</ref> This, for example, has allowed bugs in the [[Intel Core 2]] and Intel [[Xeon]] microcodes to be fixed by patching their microprograms, rather than requiring the entire chips to be replaced. A second prominent example is the set of microcode patches that Intel offered for some of their processor architectures of up to 10 years in age, in a bid to counter the security vulnerabilities discovered in their designs – [[Spectre (security vulnerability)|Spectre]] and [[Meltdown (security vulnerability)|Meltdown]] – which went public at the start of 2018.<ref>[http://www.tomshardware.com/news/intel-meltdown-spectre-patch-silicon,36672.html Intel Patches All Recent CPUs, Promises Hardware Fixes For Upcoming 8th Gen Chips] by Paul Alcorn on March 15, 2018</ref><ref>{{cite web |url=https://downloadcenter.intel.com/download/27591/Linux-Processor-Microcode-Data-File |title=Download Linux* Processor Microcode Data File |access-date=2018-03-21 |url-status=dead |archive-url=https://web.archive.org/web/20180319202103/https://downloadcenter.intel.com/download/27591/Linux-Processor-Microcode-Data-File |archive-date=2018-03-19}}</ref> A microcode update can be installed by Linux,<ref>{{cite web |url=http://urbanmyth.org/microcode/ |title=Intel Microcode Update Utility for Linux |archive-url=https://web.archive.org/web/20120226174302/http://urbanmyth.org/microcode/ |archive-date=2012-02-26 |url-status=dead}}</ref> [[FreeBSD]],<ref>{{cite web |url=https://svnweb.freebsd.org/ports/head/sysutils/cpupdate/ |title=[ports] Index of /head/sysutils/cpupdate |publisher=Freebsd.org |access-date=2020-01-16 |url-status=live |archive-url=https://web.archive.org/web/20200401215701/https://svnweb.freebsd.org/ports/head/sysutils/cpupdate/ |archive-date=2020-04-01}}</ref> Microsoft Windows,<ref>{{Cite news |url=http://support.microsoft.com/kb/936357 |title=A microcode reliability update is available that improves the reliability of systems that use Intel processors |access-date=2008-02-25 |url-status=live |archive-url=https://web.archive.org/web/20080223074207/http://support.microsoft.com/kb/936357 |archive-date=2008-02-23}}</ref> or the motherboard BIOS.<ref>{{cite web |url=http://www.intel.com/support/motherboards/server/sb/cs-021619.htm |title=Server Products - BIOS Update required when Missing Microcode message is seen during POST |date=January 24, 2013 |website=Intel |archive-url=https://web.archive.org/web/20140901063251/http://www.intel.com/support/motherboards/server/sb/cs-021619.htm |archive-date=September 1, 2014}}</ref>

Some machines offer user-programmable writable control stores as an option, including the [[HP 2100]], DEC [[PDP-11|PDP-11/60]], [[TI-990]]/12,<ref>{{cite web |title=Model 990/12 LR Computer Depot Maintenance and Repair Manual |url=http://www.bitsavers.org/pdf/ti/990/990-12/2268241_990-12CPU_DepoRepair_Feb83.pdf |website=Bitsavers.org |publisher=Texas Instruments |access-date=15 February 2024}}</ref><ref>{{cite book |title=Texas Instruments Model 990 Computer MDS-990 Microcode Development System Programmer's Guide |___location=Texas Instruments Archives, RG-20 accession 94-08, Box 10, 45C. DeGolyer Library, Southern Methodist University, Dallas, TX USA |edition=15 August 1979}}</ref> and [[Varian Data Machines]] V-70 series [[minicomputer]]s. WCS options extended down to microprocessors too. The [[PDP-11#LSI-11|DEC LSI-11]] has an option to allow programming of the internal 8-bit micromachine to create application-specific extensions to the instruction set.<ref>{{cite book |title=LSI-11 WCS user's guide |date=June 1978 |publisher=Digital Equipment Corporation |edition=1st |url=http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-KUV11-TM_LSI11_WCS.pdf |access-date=7 January 2023 |archive-date=23 February 2023 |archive-url=https://web.archive.org/web/20230223212303/http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-KUV11-TM_LSI11_WCS.pdf |url-status=live }}</ref>

==Comparison to VLIW and RISC==

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==Micro-operations==

Modern CISC implementations, such as the [[x86]] family starting with the [[NexGen]] Nx586, Intel [[Pentium Pro]], and [[AMD K5]]., decode instructions into dynamically buffered [[micro-operation]]s with an instruction encoding similar to RISC or traditional microcode. A hardwired instruction decode unit directly emits microoperations for common x86 instructions, but falls back to a more traditional microcode ROM containing microoperations for more complex or rarely used instructions.<ref name=FogMicro/>

For example, an x86 might look up microoperations from microcode to handle complex multistep operations such as loop or string instructions, [[floating-point unit]] [[transcendental function]]s or unusual values such as [[denormal number]]s, and special-purpose instructions such as [[CPUID]].

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| access-date= June 21, 2006

| doi = 10.1109/MAHC.1988.10039 |s2cid = 16405547

| url-access= subscription

}}

* {{cite web

| author = Smotherman, Mark

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| access-date = August 7, 2006

| doi = 10.1109/MAHC.1986.10035 |s2cid = 1978847

| url-access= subscription

}}

* {{cite journal

|last1=Wilkes |first1=M. V. |author1-link=Maurice Wilkes |last2=Stringer |first2=J. B. |author2-link=John Bentley Stringer

| date = April 1953

| title = Microprogramming and the Design of the Control Circuits in an Electronic Digital Computer

| journal = [[Mathematical Proceedings of the Cambridge Philosophical Society]]

| volume = 49

| issue = pt. 2

| pages = 230–238

| url = http://research.microsoft.com/~gbell/Computer_Structures_Principles_and_Examples/csp0174.htm

| access-date = August 23, 2006

| doi = 10.1017/S0305004100028322| bibcode = 1953PCPS...49..230W

|s2cid=62230627 }}| url-access= subscription

}}

* {{cite book

| last=Husson |first=S.S.

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| pages = 222–241

| doi = 10.1147/sj.64.0222

| url-access= subscription

}}

}}

* {{cite web |first=Ken |last=Shirriff |title=How the 8086 processor's microcode engine works |date=December 2022 |url=https://www.righto.com/2022/11/how-8086-processors-microcode-engine.html}}

==External links==

{{Wiktionary}}

{{External links|date=February 2017}}

* [http://c2.com/cgi/wiki?WritableInstructionSetComputer Writable Instruction Set Computer]

* [http://www.research.ibm.com/journal/rd/102/ibmrd1002F.pdf Capacitor Read-only Store]

* [https://web.archive.org/web/20050124004424/http://www-03.ibm.com/ibm/history/exhibits/attic3/attic3_016.html Transformer Read-only Store]

* [http://people.cs.clemson.edu/~mark/uprog.html A Brief History of Microprogramming]

* [https://lists.debian.org/debian-user/2013/09/msg00126.html Intel processor microcode security update] (fixes the issues when running 32-bit virtual machines in PAE mode)

* [https://web.archive.org/web/20150907195925/http://inertiawar.com/microcode/hawkes_intel_microcode.pdf Notes on Intel Microcode Updates], March 2013, by Ben Hawkes, archived from the original on September 7, 2015

* [https://web.archive.org/web/20030309102752/http://www.eetimes.com/news/97/963news/hole.html Hole seen in Intel's bug-busting feature], ''[[EE Times]]'', 2002, by Alexander Wolfe, archived from the original on March 9, 2003

* [http://www.securiteam.com/securityreviews/5FP0M1PDFO.html Opteron Exposed: Reverse Engineering AMD K8 Microcode Updates], July 26, 2004

* [https://ieeexplore.ieee.org/document/8662722 WepSIM: An Online Interactive Educational Simulator Integrating Microdesign, Microprogramming, and Assembly Language Programming], July 26, 2022

{{Processor technologies}}