IBM System/360 architecture: Difference between revisions

Revision as of 19:03, 23 January 2025

Latest revision as of 11:51, 27 July 2025

(7 intermediate revisions by 5 users not shown)

Line 79:

| style="border-style: none;" |

{| class="wikitable" style="font-size:75%"

|+ Floating Point Registers 0-, 2, 4 and 6

|-

| colspan=34 style="border-style: none;" | <br>

Line 319:

|

{| class="wikitable mw-collapsible autocollapse"

|+ style="text-align: left; font-size:95%" | {{nowrap|Program Mask}}

! Bit

! Meaning

Line 359:

Memory (''storage'') in System/360 is addressed in terms of [[8-bit]] bytes. Various instructions operate on larger units called ''halfword'' (2 bytes), ''fullword'' (4 bytes), ''doubleword'' (8 bytes), ''quad word'' (16 bytes) and 2048 byte storage block, specifying the leftmost (lowest address) of the unit. Within a halfword, fullword, doubleword or quadword, low numbered bytes are more significant than high numbered bytes; this is sometimes referred to as [[big-endian]]. Many uses for these units require aligning them on the corresponding boundaries. Within this article the unqualified term ''word'' refers to a ''fullword''.

The original architecture of System/360 provided for up to 2²⁴&nbsp;= 16,777,216 bytes of memory. The later [[IBM System/360 Model 67|Model 67]] extended the architecture to allow up to 2³²&nbsp;= 4,294,967,296<ref group=NB>{{efn|Twice the size of the later System/370</ref>}} bytes of virtual memory.

==Addressing==

Line 369:

| publisher = Sperry Rand Corporation

}}

</ref> That means that instructions do not contain complete addresses, but rather specify a base register and a positive offset from the addresses in the base registers. In the case of System/360 the base address is contained in one of 15<ref group=NB>{{efn|A specification of general register 0 yield a base address of zero rather than the register content.</ref>}} general registers. In some instructions, for example shifts, the same computations are performed for 32-bit quantities that are not addresses.

==Data formats==

Line 404:

| align=center valign=top | 0-7

| valign=top style="align:left;" | {{anchor|System_Mask}}System Mask

| valign=top | bits 0-5: enable channels 0-5, bit 6: enable all remaining channels,{{#tag:refefn|On a processor that complies with the S/360 architecture, the highest channel number is 6. Eleven bits are sufficient to identify the cuu, and seven bits are sufficient to provide masking of I/O interruptions. However, on a 360/67-2 with two 2846 channel controllers, channels are numbered 0-6 and 8-14;<ref name=GA27-2719/>{{rp|page=15}} similarly, the 360/195 had an extended channel feature<ref name=A22-6943/>{{rp|page=21}} but numbered the channels 0 through 13.<ref name=A22-6943/>{{rp|page=25}} I/O interruptions for Channel Controller 1 on the 360/67-2 were masked using control registers, and the 360/195 used bit 7 (Channel 6) of the System Mask as a summary mask bit for channels 6 and up. ''Interruptions from More than Seven Channels''{{sfn|PoOps|p=121.4}} describes the summary masking for additional channels, but other text in Principles of Operation still refers to a limit of 7 channels. Standard software supported channels 0-F.|group=NB|name=ChanNum}} bit 7: enable External interruptions (timer, interrupt key, and external signal{{sfn|PoOps|page=71}}

|-

| align=center valign=top | 8-11

Line 412:

| align=center valign=top | 12{{anchor|AMWP}}

| valign=top | ASCII mode

| enable ASCII mode for packed decimal instructions, never used by IBM software<ref group=NB>{{efn|Because the design of the S/360 occurred simultaneously with the development of ASCII, IBM's ASCII support did not match the standard that was ultimately adopted.</ref>}}

|-

| align=center valign=top | 13

Line 451:

==Interruption system==

The architecture<ref name=A22-6821-7/>{{rp|pages=77–83}} defines 5 classes of [[interrupt]]ion. An interruption is a mechanism for automatically changing the program state; it is used for both synchronous<ref group=NB>{{efn|The S/360 literature does not use the terms fault or [[Trap (computing)|trap]]</ref>}} and [[asynchrony (computing)|asynchronous]] events.

{| class="wikitable" collapsiblestyle="text-align: right;"

|-

! rowspan="2" | Interruption class !! colspan="2" | Old PSW !! colspan="2" | New PSW

! rowspan="2" | Priority

|-

! Interruption classhex !! Olddec PSW<br!! />hex dec !! New PSW<br />hex dec

! align=right valign=top | Priority

|-

| [[#Input/Output interruption|Input/Output]]{{sfn|PoOps|pp=78-79}} || 38&nbsp;&nbsp;&nbsp; || 56 || 78&nbsp;&nbsp;120 || align=right120 || 4

|-

| [[#Program interruption|Program]]{{sfn|PoOps|pp=79–80.1}} || 28&nbsp;&nbsp;&nbsp; || 40 || 68&nbsp;104 || align=right104 || 2

|-

| [[#Supervisor Call interruption|Supervisor Call]]{{sfn|PoOps|pp=80.1–81}} || 20&nbsp;&nbsp;&nbsp; || 32 || 60&nbsp;&nbsp;&nbsp;96 || align=right96 || 2

|-

| [[#External interruption|External]]{{sfn|PoOps|pp=81–82}} || 18&nbsp;&nbsp;&nbsp; || 24 || 58&nbsp;&nbsp;&nbsp;88 || align=right88 || 3

|-

| [[#Machine Check interruption|Machine Check]]{{sfn|PoOps|pp=82–83}} || 30&nbsp;&nbsp;&nbsp; || 48 || 70&nbsp;&nbsp;112 || align=right112 || 1

|}

Line 477 ⟶ 479:

===Program interruption===

A Program interruption<ref name=A22-6821-7/>{{rp|pages=16,79–80.1}} occurs when an instruction encounters one{{#tag:refefn|On the 360/91,<ref name=A22-6907/>{{rp|page=15}} 360/95 and 360/195<ref name=A22-6943/>{{rp|page=14}} a Program interruption may occur for multiple imprecise exceptions. The ILC in the Program Old PSW is 0, bits 26-31 are 0 and bits 16-27 are a mask indicating which exceptions occurred; there is no provision for reporting multiple occurrences of the same exception. Reporting of multiple imprecise exceptions is not part of the S/360 architecture.|group=NB|name=multimpr}} of 15{{#tag:refefn|There are 17 possible exceptions on the 360/67,<ref name=GA27-2719/>{{rp|page=17}} but page exception and segment exception are not part of the S/360 architecture; similarly, interruption code 18 ('0012'X) on a 360/65 multiprocessor is not part of the S/360 architecture.|group=NB|name=NotArchExc}} exceptions; however, if the [[#Program Mask|Program Mask]] bit corresponding to an exception is 0 then there is no interruption for that exception.

On 360/65,<ref name=A22-6884/>{{rp|page=12}} 360/67<ref name=GA27-2719/>{{rp|page=46}} and 360/85<ref name=A22-6916/>{{rp|page=12}} the Protection Exception and Addressing Exception interruptions can be imprecise, in which case they store an Instruction Length Code of 0.

The Interruption code may be any of

Line 491 ⟶ 493:

| align=right valign=top | 0

|

Imprecise interruption<ref group=NB {{efn|name=multimpr/>}} on 360/91,<ref name=A22-6907/>{{rp|page=15}} 360/95 or 360/195<ref name=A22-6943/>{{rp|page=14}}

{| class="wikitable collapsible collapsed"

|+ {{nowrap|Old PSW bits for multiple imprecise interruption codes}}

Line 505 ⟶ 507:

|-

| 18

| Specification<ref group=NB>{{efn|The Specification bit is not used for imprecise interruptions on the 360/195</ref>}}

|-

| 19

Line 529 ⟶ 531:

|-

| 26

| Decimal Overflow<ref group=NB {{efn|name=NoDec>|Not Used on 360/91</ref>}}

|-

| 27

| Decimal Divide<ref group=NB {{efn|name=NoDec/>}}

|}

|-

Line 598 ⟶ 600:

| align=right | 16

|

Segment Translation<ref name=GA27-2719/>{{rp|page=17}}<ref group=NB {{efn|name=NotArchExc/>}}

|-

| align=right | 11

| align=right | 17

|

Page Translation<ref name=GA27-2719/>{{rp|page=17}}<ref group=NB {{efn|name=NotArchExc/>}}

|-

| align=right | 12

| align=right | 18

|

SSM Exception<ref name=A22-6884/><ref group=NB {{efn|name=NotArchExc/>}}

|}

Line 614 ⟶ 616:

* A '''privileged operation exception'''{{sfn|PoOps|p=79}} is recognized when a program attempts to execute a privileged instruction when the problem state bit in the PSW is 1.

* An '''execute exception'''{{sfn|PoOps|p=79}} is recognized when the operand of an [[Execute instruction|EXECUTE instruction (EX)]] is another EXECUTE instruction.

* A '''protection exception'''{{sfn|PoOps|p=79}} is recognized when a program attempts to store into a ___location whose storage protect key does not match<ref group=NB>{{efn|A PSW key of 0 matches any storage key.</ref>}} the PSW key, or to fetch from a fetch protected ___location whose storage protect key does not match the PSW key.

* An '''addressing exception'''{{sfn|PoOps|pp=79–80}} is recognized when a program attempts to access a storage ___location that is not currently available. This normally occurs with an address beyond the capacity of the machine, but it may also occur on machines that allow blocks of storage to be taken offline.

*A '''specification exception'''{{sfn|PoOps|p=80}} is recognized when an instruction has a length or register field with values not permitted by the operation, or when it has an operand address that does not satisfy the alignment requirements of the opcode, e.g., a LH instruction with an odd operand address on a machine without the byte alignment feature.

Line 631 ⟶ 633:

===External interruption===

An External{{sfn|PoOps|p=81}}<ref group=NB>{{efn|Even though a timer expiration is an internal event, it causes an External interruption and for this reason, this interruption is usually referred to as a timer/external interruption.</ref>}} interruption occurs as the result of certain asynchronous events. Bits 16-24 of the External Old PSW are set to 0 and one or more of bits 24-31 is set to 1

{| class="wikitable collapsible"

Line 693 ⟶ 695:

* {{anchor|IBM_Byte_Mux}}A '''byte multiplexer channel''' is capable of executing multiple '''CCW'''s concurrently; it is normally used to attach slow devices such as card readers and telecommunications lines. A byte multiplexer channel could have a number of selector subchannels, each with only a single subchannel, which behave like low-speed selector channels.

* {{anchor|IBM_Sel}}A '''selector channel''' has only a single subchannel, and hence is only capable of executing one channel command at a time. It is normally used to attach fast devices that are not capable of exploiting a block multiplexer channel to suspend the connection, such as magnetic tape drives.

* {{anchor|IBM_Blk_Mux}}A '''block multiplexer channel''' is capable of concurrently running multiple channel programs, but only one at a time can be active. The control unit can request suspension at the end of a channel command and can later request resumption. This is intended for devices in which there is a mechanical delay after completion of data transfer, e.g., for seeks on moving-head DASD. The block multiplexer channel was a late addition to the System/360 architecture; early machines had only byte multiplexer channels and selector channels. The block multiplexer channel wasis an optional feature only on the models 85 and 195. The block multiplexor channel wasis also available on the later [[IBM System/370|System/370]] computers.

Conceptually peripheral equipment is attached to a S/360 through ''control units'', which in turn are attached through channels. However, the architecture does not require that control units be physically distinct, and in practice they are sometimes integrated with the devices that they control. Similarly, the architecture does not require the channels to be physically distinct from the processor, and the smaller S/360 models (through 360/50) have integrated channels that [[Cycle stealing|steal cycles]] from the processor.

Peripheral devices are addressed with 16-bit<ref group=NB>{{efn|Because of the limits on the channel number, S/360 and early S/370 software only used 12 bits to store device addresses.</ref>}} addresses.,<ref name=A22-6821-7/>{{rp|page=89}} referred to as ''cua'' or ''cuu''; this article will use the term ''cuu''. The high 8 bits identify a channel, numbered from 0 to 6,<ref group=NB {{efn|name=ChanNum/>}} while the low 8 bits identify a device on that channel. A device may have multiple ''cuu'' addresses.

Control units are assigned an address "capture" range. For example, a CU might be assigned range 20-2F or 40-7F. The purpose of this is to assist with the connection and prioritization of multiple control units to a channel. For example, a channel might have three disk control units at 20-2F, 50-5F, and 80-8F. Not all of the captured addresses need to have an assigned physical device. Each control unit is also marked as High or Low priority on the channel.

Device selection progresses from the channel to each control unit in the order they are physically attached to their channel. At the end of the chain the selection process continues in reverse back towards the channel. If the selection returns to the channel then no control unit accepted the command and SIO returns Condition Code 3. Control units marked as High Priority check the outbound CUU to be within their range. If so, then the I/O wasis processed. If not, then the selection wasis passed to the next outbound CU. Control units marked as Low Priority check for inbound (returning) CUU to be within their range. If so, then the I/O is processed. If not, then the selection is passed to the next inbound CU (or the channel). The connection of three controls unit to a channel might be physically -A-B-C and, if all are marked as High then the priority would be ABC. If all are marked low then the priority would be CBA. If B was marked High and AC low then the order would be BCA. Extending this line of reasoning then the first of N controllers would be priority 1 (High) or 2N-1 (Low), the second priority 2 or 2N-2, the third priority 3 or 2N-3, etc. The last physically attached would always be priority N.

There are three storage fields reserved for I/O; a double word I/O old PSW, a doubleword I/O new PSW and a fullword ''Channel Address Word'' ('''CAW'''). Performing an I/O normally requires the following:

* initializing the '''CAW''' with the storage key and the address of the first CCW

* issuing a ''Start I/O'' ('''SIO''') instruction that specifies the ''cuu'' for the operation

* waiting<ref group=NB>{{efn|But continuing with unrelated work.</ref>}} for an I/O interruption

* handling any unusual conditions indicated in the ''Channel Status Word'' ('''CSW''')

Line 735 ⟶ 737:

These conditions are presented to the channel by the control unit or device.{{sfn|PoOps|pp=113–116}} In some cases they are handled by the channel and in other cases they are indicated in the [[#Channel Status Word|CSW]]. There is no distinction between conditions detected by the control unit and conditions detected by the device.

* {{Anchor|Attention}}'''[[#CSW_Attention|Attention]]'''{{sfn|PoOps|p=113}} indicates an unusual condition not associated with an ongoing channel program. It often indicates some sort of operator action like requesting input, in which case the CPU would respond by issuing a read-type command, most often a sense command (04h) from which additional information could be deduced. Attention is a special condition, and requires specific operating system support, and for which the operating system has a special attention table<ref group=NB>{{efn|The OS uses the attention index in a [[Unit Control Block]] (UCB) as an index into the attention table.</ref>}} with a necessarily limited number of entries.

* {{Anchor|Status modifier|SM}}'''[[#CSW_Status_modifier|Status modifier]]'''{{sfn|PoOps|pp=113–114}} (SM) indicates one of three unusual conditions

** A Test I/O instruction was issued to a device that does not support it.

Line 754 ⟶ 756:

* {{Anchor|Channel end|CE}}'''[[#CSW_Channel_end|Channel end]]'''{{sfn|PoOps|p=115}} indicates that the device has completed the data transfer for a channel command. There may also be an [[#Incorrect length|Incorrect length]] indication if the Count field of the CCW is exhausted, depending on the value of the [[#CCW-SuppressLengthIndication|Suppress-Length-Indication]] bit.

* {{Anchor|Device end|DE}}'''[[#CSW_Device_end|Device end]]'''{{sfn|PoOps|p=115}} indicates that the device has completed an operation and is ready to accept another. DE may be signalled concurrently with [[#Channel en|CE]] or may be delayed.

* {{Anchor|Unit check|UC}}'''[[#CSW_Unit_check|Unit check]]'''{{sfn|PoOps|pp=115–116}} indicates that the device or control unit has detected an unusual conditionscondition and that details may be obtained by issuing a Sense command.

* {{Anchor|Unit exception|UE}}'''[[#CSW_Unit_exception|Unit exception]]'''{{sfn|PoOps|p=116}} indicates that the device has detected an unusual condition, e.g., end of file.

Line 828 ⟶ 830:

|-

| align=right valign=top | 34

| valign=top | {{anchor|CCW-SLI}}SLI<ref group=NB>{{efn|Also known as Suppress Incorrect Length Indication (SILI)</ref>}}

| valign=top | {{anchor|CCW-SuppressLengthindication}}Suppress-Length-Indication

| Continue channel program after count mis-match.{{sfn|PoOps|pp=99–100}}

Line 971 ⟶ 973:

* '''{{anchor|Initial_Program_Load}}Initial Program Load''' (IPL){{sfn|PoOps|p=123}} is a process for loading a program when there isn't a loader available in storage, usually because the machine was just powered on or to load an alternative operating system.<ref name=A22-6821-7/>{{rp|page=123}} This process is sometimes known as [[Booting]].

:: As part of the IPL facility the operator has a means of specifying a 12-bit<ref group=NB {{efn|name=ChanNum/>}} device address, typically with three dials as shown in the operator controls drawing. When the operator<ref group=NB>{{efn|Or an equivalent automated facility.</ref>}} selects the ''Load'' function, the system performs a ''System Reset'', sends a Read IPL<ref group=NB>{{efn|Read with all modifier bits zero</ref>}} channel command to the selected device in order to read 24 bytes into locations 0-23 and causes the channel to begin fetching ''CCW''s at ___location 8; the effect is as if the channel had fetched a CCW from ___location 0 with a length of 24, andan address of 0 and the flags containing Command Chaining + Suppress Length Indication. At the completion of the operation, the system stores the I/O address in the halfword at ___location 2 and loads the PSW from ___location 0.

:: Initial program loading is typically done from a tape, a card reader, or a disk drive. Generally, the operating system was loaded from a disk drive; IPL from tape or cards was used only for diagnostics or for installing an operating system on a new computer.

Line 1,046 ⟶ 1,048:

==Notes==

{{Reflist|group=NB}}

{{notelist}}