Cache hierarchy: Difference between revisions

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In a banked cache, the cache is divided into a cache dedicated to [[machine code|instruction]] storage and a cache dedicated to data. In contrast, a unified cache contains both the instructions and data in the same cache.<ref>Yan Solihin, 2015. Fundamentals of Parallel Multicore Architecture. CRC Press. p. 150. {{ISBN|978-1-4822-1119-1}}.</ref> During a process, the L1 cache (or most upper-level cache in relation to its connection to the processor) is accessed by the processor to retrieve both instructions and data. Requiring both actions to be implemented at the same time requires multiple ports and more access time in a unified cache. Having multiple ports requires additional hardware and wiring, leading to a significant structure between the caches and processing units.<ref>Steve Heath, 2002. Embedded Systems Design. Elsevier. p. 106. {{ISBN|978-0-08-047756-5}}.</ref> To avoid this, the L1 cache is often organized as a banked cache which results in fewer ports, less hardware, and generally lower access times.<ref name=":1" />

Modern processors have split caches, and in systems with multilevel caches higherlower level caches may be unified while lowerhigher levels split.<ref name="CA:QA" /><ref>Alan Clements, 2013. Computer Organization & Architecture: Themes and Variations. Cengage Learning. p. 588. {{ISBN|1-285-41542-6}}.</ref>

=== Inclusion policies ===

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=== Intel i5 Raptor Lake-HX (2024) ===

6-core (performance | efficiency):

* L1 cache – 128&nbsp;{{abbr|KB|kilobytes}} per core

* L2 cache – 2&nbsp;{{abbr|MB|megabytes}} per core | 4–8&nbsp;{{abbr|MB|megabytes}} semi-shared

* L3 cache – 20–24&nbsp;{{abbr|MB|megabytes}} shared

=== AMD EPYC 9684X (Zen 4, 2023) ===

96-core:

* L1 cache – 64&nbsp;{{abbr|KB|kilobytes}} per core

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* L3 cache – 96&nbsp;{{abbr|MB|megabytes}} shared

=== AMD RyzenZen 70003 (2022) ===

6- to 16-core:

* L1 cache – 64&nbsp;{{abbr|KB|kilobytes}} per core

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* L3 cache – 32 to 128&nbsp;{{abbr|MB|megabytes}} shared

=== AMD Zen 2 microarchitecture (2019) ===

* L1 cache – 32&nbsp;KB data & 32 KB instruction per core, 8-way

* L2 cache – 512&nbsp;KB per core, 8-way inclusive

* L3 cache – 16 MB local per 4-core CCX, 2 CCXs per chiplet, 16-way non-inclusive. Up to 64 MB on desktop CPUs and 256 MB on server CPUs

=== AMD Zen microarchitecture (2017) ===

* L1 cache – 32&nbsp;KB data & 64 KB instruction per core, 4-way

* L2 cache – 512&nbsp;KB per core, 4-way inclusive

* L3 cache – 4 MB local & remote per 4-core CCX, 2 CCXs per chiplet, 16-way non-inclusive. Up to 16 MB on desktop CPUs and 64 MB on server CPUs

=== Intel Kaby Lake microarchitecture (2016) ===

* L1 cache (instruction and data) – 64&nbsp;KB per core

* L2 cache – 256&nbsp;KB per core

* L3 cache – 2&nbsp;MB to 8&nbsp;MB shared<ref name=":3">{{Cite web|url=https://ark.intel.com/|title=Intel Kaby Lake Microrchitecture}}</ref>

=== Intel Broadwell microarchitecture (2014) ===

* L1 cache (instruction and data) – 64&nbsp;{{abbr|KB|kilobytes}} per core

* L2 cache – 256&nbsp;KK per core

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== See also ==

* CPU microarchitectures mentioned in this article:

** [[POWER7]]

** [[Broadwell (microarchitecture)|Intel Broadwell Microarchitecture]]

* [[Kaby Lake|Intel Kaby Lake Microarchitecture]]

** [[Zen (microarchitecture)|AMD Zen]]

** [[Apple silicon|Apple Silicon]]

* [[CPU cache]]

* [[Memory hierarchy]]

* [[CAS latency|CAS latency (RAM)]]

* [[Cache (computing)]]