Comparison of instruction set architectures: Difference between revisions

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{{Short description|none}} <!-- This short description is INTENTIONALLY "none" - please see WP:SDNONE before you consider changing it! -->

An '''[[instruction set architecture]]''' ('''ISA''') is an abstract model of a [[computer]], also referred to as '''computer architecture'''. A realization of an ISA is called an ''implementation''. An ISA permits multiple implementations that may vary in [[Computer performance|performance]], physical size, and monetary cost (among other things); because the ISA serves as the [[Interface (computing)|interface]] between [[software]] and [[Computer hardware|hardware]]., Softwaresoftware that has been written or compiled for an ISA can run on different implementations of the same ISA. This has enabled [[binary compatibility]] between different generations of computers to be easily achieved, and the development of computer families. Both of these developments have helped to lower the cost of computers and to increase their applicability. For these reasons, the ISA is one of the most important abstractions in [[computing]] today.

An ISA defines everything a [[machine language]] [[programmer]] needs to know in order to program a computer. What an ISA defines differs between ISAs; in general, ISAs define the supported [[data type]]s, what state there is (such as the [[main memory]] and [[Processor register|register]]s) and their semantics (such as the [[memory consistency]] and [[addressing mode]]s), the ''instruction set'' (the set of [[machine instruction]]s that comprises a computer's machine language), and the [[input/output]] model.

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=== Bits ===

[[Computer architecture]]s are often described as ''n''-[[bit]] architectures. In the first {{frac|3|4}} of the 20th century, ''n'' is often [[12-bit computing|12]], [[18-bit computing|18]], [[24-bit computing|24]], 30, [[36-bit computing|36]], [[48-bit computing|48]] or [[60-bit computing|60]]. In the last {{frac|1|3}} of the 20th century, ''n'' is often 8, 16, or 32, and in the 21st century, ''n'' is often 16, 32 or 64, but other sizes have been used (including 6, [[Elliott 803|39]], [[128-bit computing|128]]). This is actually a simplification as computer architecture often has a few more or less "natural" data sizes in the [[instruction set]], but the hardware implementation of these may be very different. Many instruction set architectures have instructions that, on some implementations of that instruction set architecture, operate on half and/or twice the size of the processor's major internal datapaths. Examples of this are the [[Z80]], [[MC68000]], and the [[IBM System/360]]. On these types of implementations, a twice as wide operation typically also takes around twice as many clock cycles (which is not the case on high performance implementations). On the 68000, for instance, this means 8 instead of 4 clock ticks, and this particular chip may be described as a [[32-bit computing|32-bit]] architecture with a [[16-bit computing|16-bit]] implementation. The IBM System/360 instruction set architecture is 32-bit, but several models of the System/360 series, such as the [[IBM System/360 Model 30]], have smaller internal data paths, while others, such as the [[360/195]], have larger internal data paths. The external databus width is not used to determine the width of the architecture; the [[NS320xx|NS32008, NS32016 and NS32032]] were basically the same 32-bit chip with different external data buses;. theIBM's NS32764[[PowerPC_600#PowerPC_604|PowerPC had604]] has a [[64-bit computing|64-bit]] bus, andbut usedonly 32-bit registerregisters. Early 32-bit microprocessors often had a 24-bit address, as did the System/360 processors. Initial versions of [[SuperH]] had a fixed-length 16-bit instructions in spite of having a 32-bit architecture, while later versions were 32-bit.

=== Digits ===

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=== Opcodes ===

{{main|Opcode}}

In some architectures, an instruction has a single opcode. In others, some instructions have an opcode and one or more modifiers. E.g., on the [[IBM System/370]], byte 0 is the opcode but when byte 0 is a {{base|B2|16}} then byte 1 selects a specific instruction, e.g., {{base|B205|16}} is store clock (STCK). On some instruction set architectures, one or more [[opcode prefix]]es are used to alter the subsequent opcode or expand the number of opcodes.

=== Operands ===

==== Addressing modes ====

{{main|addressingAddressing mode}}

Architectures typically allow instructions to include some combination of operand [[addressing mode]]s:

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:The instruction specifies the ___location of a pointer word that describes the operand, possibly involving multiple levels of indexing and indirection

;Truncated

:The instruction specifies the low order bits and a register provides the high order bits.

;Base-displacement

:The instruction specifies a displacement from an address in a register

;autoincrement/autodecrement

:A register used for indexing, or a pointer word used by indirect addressing, is incremented or decremented by 1, an operand size or an explicit delta

Vector processors have offered [[Vector_processor#Vector_processor_features|additional modes]] unique to element-based operations.

==== Number of operands ====

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! {{verth|[[Endianness]]}}

! Extensions

! [[Open-source hardware|Open]]

! Open

! Royalty<br />free

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| [[ARM architecture#64/32-bit architecture|Arm64/A64]]

| 64

| v8.9-A/v9.4-A,<br/><ref>{{Cite web |title=Arm A-Profile Architecture Developments 2022 - Architectures and Processors blog - Arm Community blogs - Arm Community |url=https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-2022 |access-date=2022-12-09 |website=community.arm.com |date=29 September 2022 |language=en}}</ref> Armv8-R<br/><ref>{{cite news |last=Frumusanu |first=Andrei |date=September 3, 2020 |url=https://www.anandtech.com/show/16056/arm-announces-cortexr82-first-64bit-real-time-processor |archive-url=https://web.archive.org/web/20200903134024/https://www.anandtech.com/show/16056/arm-announces-cortexr82-first-64bit-real-time-processor |url-status=dead |archive-date=September 3, 2020 |title=ARM Announced Cortex-R82: First 64-bit Real Time Processor |website=[[AnandTech]]}}</ref>

| 2011<br/><ref>{{cite web |url= https://www.computerworld.com/article/1536136/arm-goes-64-bit-with-new-armv8-chip-architecture.html |title= ARM goes 64-bit with new ARMv8 chip architecture |website=[[Computerworld]] |date= 27 October 2011 |access-date= 8 May 2024}}</ref>

| 3

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| Bi

| [[AltiVec]], APU, [[AltiVec#VSX|VSX]], [[Cell (microprocessor)|Cell]], Floating-point, Matrix Multiply Assist

| Licensed by [[OpenPOWER_Foundation|OPF]] <!-- Commercial use requires Licensing. exemptions for GPGAs. see EULA-->

| {{Yes}}

| Only if Licensed<ref>[https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/ Final draft of Power ISA EULA]</ref>

| {{Yes}}

|-

| [[RISC-V]]