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{{Program execution}}
In [[processor design]], '''microcode''' serves as an intermediary layer situated between the [[central processing unit]] (CPU) hardware and the programmer-visible [[instruction set architecture]] of a computer.<ref name="Kent2813">{{cite book |last1=Kent |first1=Allen |url=https://books.google.com/books?id=EjWV8J8CQEYC |title=Encyclopedia of Computer Science and Technology: Volume 28 - Supplement 13 |last2=Williams |first2=James G. |date=April 5, 1993 |publisher=Marcel Dekker, Inc |isbn=0-8247-2281-7 |___location=New York |page=34 |access-date=Jan 17, 2016 |archive-url=https://web.archive.org/web/20161120161636/https://books.google.com/books?id=EjWV8J8CQEYC |archive-date=November 20, 2016 |url-status=live}}</ref>
Housed in special high-speed memory, microcode translates machine instructions, [[state machine]] data, or other input into sequences of detailed circuit-level operations. It separates the machine instructions from the underlying [[electronics]], thereby enabling greater flexibility in designing and altering instructions. Moreover, it facilitates the construction of complex multi-step instructions, while simultaneously reducing the complexity of computer circuits. The act of writing microcode is often referred to as ''microprogramming'', and the microcode in a specific processor implementation is sometimes termed a ''microprogram''.
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To properly perform an instruction, the various circuits have to be activated in order. For instance, it is not possible to add two numbers if they have not yet been loaded from memory. In [[RISC]] designs, the proper ordering of these instructions is largely up to the programmer, or at least to the [[compiler]] of the [[programming language]] they are using. So to add two numbers, for instance, the compiler may output instructions to load one of the values into one register, the second into another, call the addition function in the ALU, and then write the result back out to memory.<ref name=CPU/>
As the sequence of instructions needed to complete this higher-level concept, "add these two numbers in memory", may require multiple instructions, this can represent a performance bottleneck if those instructions are stored in [[main memory]]. Reading those instructions one by one
Using the variation of the instruction, or "[[opcode]]", that most closely matches the ultimate operation can reduce the number of instructions to one, saving memory used by the program code and improving performance by leaving the [[data bus]] open for other operations. Internally, however, these instructions are not separate operations, but sequences of the operations the units actually perform. Converting a single instruction read from memory into the sequence of internal actions is the duty of the [[control unit]], another unit within the processor.<ref name=microcode>{{cite web |url=http://www.righto.com/2022/11/how-8086-processors-microcode-engine.html#:~:text=In%201951%2C%20Maurice%20Wilkes%20came,memory%20called%20a%20control%20store. |title=How the 8086 processor's microcode engine works |website=Ken Shirriff's blog |first=Ken |last=Shirriff}}</ref>
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==History==
===Early examples===
The ACE computer, designed by [[Alan Turing]] in 1946, used microprogramming.<ref>{{cite book | title=Modern Mathematics | date=2006 | publisher=Infobase | isbn=978-0-7910-9720-5 | url=https://books.google.com/books?id=5LMVSFNhFI0C&dq=ace+microprogramming&pg=PA121 }}</ref>
In 1947, the design of the [[Whirlwind (computer)|MIT Whirlwind]] introduced the concept of a control store as a way to simplify computer design and move beyond ''[[ad hoc]]'' methods. The control store is a [[diode matrix]]: a two-dimensional lattice, where one dimension accepts "control time pulses" from the CPU's internal clock, and the other connects to control signals on gates and other circuits. A "pulse distributor" takes the pulses generated by the [[CPU clock]] and breaks them up into eight separate time pulses, each of which activates a different row of the lattice. When the row is activated, it activates the control signals connected to it.<ref>{{Cite tech report |last1=Everett |first1=R.R. |last2=Swain |first2=F.E. |year=1947 |title=Whirlwind I Computer Block Diagrams |publisher=MIT Servomechanisms Laboratory |id=R-127 |url=http://www.cryptosmith.com/wp-content/uploads/2009/05/whirlwindr-127.pdf |access-date=June 21, 2006 |url-status=dead |archive-url=https://web.archive.org/web/20120617112919/http://www.cryptosmith.com/wp-content/uploads/2009/05/whirlwindr-127.pdf |archive-date=June 17, 2012}}</ref>
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The result of this discovery was what is today known as the [[RISC]] concept. The complex microcode engine and its associated ROM is reduced or eliminated completely, and those circuits instead dedicated to things like additional registers or a wider ALU, which increases the performance of every program. When complex sequences of instructions are needed, this is left to the compiler, which is the entire purpose of using a compiler in the first place. The basic concept was soon picked up by university researchers in California, where simulations suggested such designs would trivially outperform even the fastest conventional designs. It was one such project, at the [[University of California, Berkeley]], that introduced the term RISC.
The industry responded to the concept of RISC with both confusion and hostility, including a famous dismissive article by the VAX team at Digital.<ref name=comments>{{cite journal |url=https://dl.acm.org/doi/pdf/10.1145/641914.641918 |title=Comments on "The Case for the Reduced Instruction Set Computer," by Patterson and Ditzel|first1=Douglas |last1=Clark |first2=William |last2=Strecker |date=September 1980 |journal= ACM SIGARCH Computer Architecture News|volume=8 |issue=6 |pages=34–38 |doi=10.1145/641914.641918 |s2cid=14939489 |url-access=subscription }}</ref> A major point of contention was that implementing the instructions outside of the processor meant it would spend much more time reading those instructions from memory, thereby slowing overall performance no matter how fast the CPU itself ran.<ref name=comments/> Proponents pointed out that simulations clearly showed the number of instructions was not much greater, especially when considering compiled code.<ref name=risc/>
The debate raged until the first commercial RISC designs emerged in the second half of the 1980s, which easily outperformed the most complex designs from other companies. By the late 1980s it was over; even DEC was abandoning microcode for their [[DEC Alpha]] designs, and CISC processors switched to using hardwired circuitry, rather than microcode, to perform many functions. For example, the [[Intel 80486]] uses hardwired circuitry to fetch and decode instructions, using microcode only to execute instructions; register-register move and arithmetic instructions required only one microinstruction, allowing them to be completed in one clock cycle.<ref>{{cite conference
Some processor designs use machine code that runs in a special mode, with special instructions, available only in that mode, that have access to processor-dependent hardware, to implement some low-level features of the instruction set. The DEC Alpha, a pure RISC design, used [[PALcode]] to implement features such as [[translation lookaside buffer]] (TLB) miss handling and interrupt handling,<ref name="axp-architecture-manual">{{cite book|url=http://bitsavers.org/pdf/dec/alpha/Sites_AlphaAXPArchitectureReferenceManual_2ed_1995.pdf|title=Alpha AXP Architecture Reference Manual|edition=Second|chapter=Part I / Common Architecture, Chapter 6 Common PALcode Architecture|publisher=[[Digital Press]]|date=1995|isbn=1-55558-145-5}}</ref> as well as providing, for Alpha-based systems running [[OpenVMS]], instructions requiring interlocked memory access that are similar to instructions provided by the [[VAX]] architecture.<ref name="axp-architecture-manual" /> CMOS [[IBM System/390]] CPUs, starting with the G4 processor, and [[z/Architecture]] CPUs use [[millicode]] to implement some instructions.<ref>{{cite journal|last=Rogers|first=Bob|title=The What and Why of zEnterprise Millicode|journal=IBM Systems Magazine|date=Sep–Oct 2012|url=http://www.ibmsystemsmag.com/mainframe/administrator/performance/millicode_rogers/|archive-url=https://web.archive.org/web/20121009085728/http://www.ibmsystemsmag.com/mainframe/administrator/performance/millicode_rogers/|archive-date=October 9, 2012|url-status=dead}}</ref>
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Starting with the [[Pentium Pro]] in 1995, several [[x86]] CPUs have writable [[Intel Microcode]].<ref name="Stiller_1996">{{cite journal |last1=Stiller |first1=Andreas |last2=Paul |first2=Matthias R.<!-- info contributor on processor internals --> |date=1996-05-12 |title=Prozessorgeflüster |series=Trends & News |language=de |journal=[[c't|c't – magazin für computertechnik]] |publisher=[[Heise Verlag]] |url=https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html |access-date=2017-08-28 |url-status=live |archive-url=https://web.archive.org/web/20170828172141/https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html |archive-date=2017-08-28}}</ref><ref>{{cite book |url=http://www.intel.com/Assets/PDF/manual/253668.pdf |title=Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, Part 1 |chapter=9.11: Microcode update facilities |publisher=[[Intel]] |date=September 2016}}</ref> This, for example, has allowed bugs in the [[Intel Core 2]] and Intel [[Xeon]] microcodes to be fixed by patching their microprograms, rather than requiring the entire chips to be replaced. A second prominent example is the set of microcode patches that Intel offered for some of their processor architectures of up to 10 years in age, in a bid to counter the security vulnerabilities discovered in their designs – [[Spectre (security vulnerability)|Spectre]] and [[Meltdown (security vulnerability)|Meltdown]] – which went public at the start of 2018.<ref>[http://www.tomshardware.com/news/intel-meltdown-spectre-patch-silicon,36672.html Intel Patches All Recent CPUs, Promises Hardware Fixes For Upcoming 8th Gen Chips] by Paul Alcorn on March 15, 2018</ref><ref>{{cite web |url=https://downloadcenter.intel.com/download/27591/Linux-Processor-Microcode-Data-File |title=Download Linux* Processor Microcode Data File |access-date=2018-03-21 |url-status=dead |archive-url=https://web.archive.org/web/20180319202103/https://downloadcenter.intel.com/download/27591/Linux-Processor-Microcode-Data-File |archive-date=2018-03-19}}</ref> A microcode update can be installed by Linux,<ref>{{cite web |url=http://urbanmyth.org/microcode/ |title=Intel Microcode Update Utility for Linux |archive-url=https://web.archive.org/web/20120226174302/http://urbanmyth.org/microcode/ |archive-date=2012-02-26 |url-status=dead}}</ref> [[FreeBSD]],<ref>{{cite web |url=https://svnweb.freebsd.org/ports/head/sysutils/cpupdate/ |title=[ports] Index of /head/sysutils/cpupdate |publisher=Freebsd.org |access-date=2020-01-16 |url-status=live |archive-url=https://web.archive.org/web/20200401215701/https://svnweb.freebsd.org/ports/head/sysutils/cpupdate/ |archive-date=2020-04-01}}</ref> Microsoft Windows,<ref>{{Cite news |url=http://support.microsoft.com/kb/936357 |title=A microcode reliability update is available that improves the reliability of systems that use Intel processors |access-date=2008-02-25 |url-status=live |archive-url=https://web.archive.org/web/20080223074207/http://support.microsoft.com/kb/936357 |archive-date=2008-02-23}}</ref> or the motherboard BIOS.<ref>{{cite web |url=http://www.intel.com/support/motherboards/server/sb/cs-021619.htm |title=Server Products - BIOS Update required when Missing Microcode message is seen during POST |date=January 24, 2013 |website=Intel |archive-url=https://web.archive.org/web/20140901063251/http://www.intel.com/support/motherboards/server/sb/cs-021619.htm |archive-date=September 1, 2014}}</ref>
Some machines offer user-programmable writable control stores as an option, including the [[HP 2100]], DEC [[PDP-11|PDP-11/60]], [[TI-990]]/12,<ref>{{cite web |title=Model 990/12 LR Computer Depot Maintenance and Repair Manual |url=http://www.bitsavers.org/pdf/ti/990/990-12/2268241_990-12CPU_DepoRepair_Feb83.pdf |website=Bitsavers.org |publisher=Texas Instruments |access-date=15 February 2024}}</ref><ref>{{cite book |title=Texas Instruments Model 990 Computer MDS-990 Microcode Development System Programmer's Guide |___location=Texas Instruments Archives, RG-20 accession 94-08, Box 10, 45C. DeGolyer Library, Southern Methodist University, Dallas, TX USA |edition=15 August 1979}}</ref> and [[Varian Data Machines]] V-70 series [[minicomputer]]s. WCS options extended down to microprocessors too. The [[PDP-11#LSI-11|DEC LSI-11]] has an option to allow programming of the internal 8-bit micromachine to create application-specific extensions to the instruction set.<ref>{{cite book |title=LSI-11 WCS user's guide |date=June 1978 |publisher=Digital Equipment Corporation |edition=1st |url=http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-KUV11-TM_LSI11_WCS.pdf |access-date=7 January 2023 |archive-date=23 February 2023 |archive-url=https://web.archive.org/web/20230223212303/http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-KUV11-TM_LSI11_WCS.pdf |url-status=live }}</ref>
==Comparison to VLIW and RISC==
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==External links==
{{Wiktionary}}
* [http://c2.com/cgi/wiki?WritableInstructionSetComputer Writable Instruction Set Computer]
* [http://www.research.ibm.com/journal/rd/102/ibmrd1002F.pdf Capacitor Read-only Store]
{{Processor technologies}}
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