Transaction-level modeling: Difference between revisions

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{{Short description|Approach for digital systems design}}

'''Transaction-level modeling''' ('''TLM''') is an approach to modelling complex digital systems by using [[electronic design automation]] software.<ref name="TVLSIHB-2007">{{Cite book |url=https://www.worldcat.org/oclc/70699056 |title=The VLSI handbook |date=2007 |publisher=CRC/Taylor & Francis |others=Wai-Kai Chen |isbn=978-0-8493-4199-1 |edition=2 |___location=Boca Raton, FL |oclc=70699056}}</ref>{{Rp|page=1955}} TLM is used primarily in the design and verification of complex [[System-on-a-chip|systems-on-chip]] (SoCs) and other electronic systems where traditional [[Register-transfer level|register-transfer level]] (RTL) modeling would be too slow or resource-intensive for system-level analysis. TLM language (TLML) is a [[hardware description language]], usually, written in C++ and based on [[SystemC]] library.<ref name="TVLSIHB-2007" /> TLMLs are used for modelling where details of communication among modules are separated from the details of the implementation of functional units or of the communication architecture. It's used for modelling of systems that involve complex data communication mechanisms.{{r|TVLSIHB-2007|pp=1955}} The modeling approach focuses on the ''transactions'' or ''transfers'' of data between functional blocks rather than the detailed implementation of those blocks or their interconnections.<ref name="IEEE_TLM_Standard">{{cite journal |title=IEEE Standard for Standard SystemC Language Reference Manual |journal=IEEE StdSTD 1666-2011 |year=2012 |url=https://ieeexplore.ieee.org/document/6134619 |doi=10.1109/IEEESTD.2012.6134619|isbn=978-0-7381-6801-2 }}</ref> This abstraction enables faster simulation speeds, often orders of magnitude faster than RTL, while maintaining sufficient accuracy for system-level design decisions, [[software development]], and architectural exploration.<ref name="Ghenassia_TLM">{{cite book |title=Transaction-Level Modeling with SystemC |editor=Ghenassia, Frank |publisher=Springer |year=2005 |isbn=978-0-387-26233-4}}</ref>

Components such as buses or [[FIFO (computing and electronics)|FIFOs]] are modeled as channels, and are presented to modules using [[SystemC]] interface classes. Transaction requests take place by calling interface functions of these channel models, which encapsulate low-level details of the information exchange. At the transaction level, the emphasis is more on the functionality of the data transfers – what data are transferred to and from what locations – and less on their actual implementation, that is, on the actual protocol used for data transfer. This approach makes it easier for the system-level designer to experiment, for example, with different bus architectures (all supporting a common abstract interface) without having to recode models that interact with any of the buses, provided these models interact with the bus through the common interface.<ref>T. Grötker, S. Liao, G. Martin, S. Swan, System Design with SystemC. Springer, 2002, Chapter 8., pp. 131. {{ISBN|1-4020-7072-1}} (quoted with permission)</ref>

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TLM is typically implemented using [[SystemC]], a [[C++]]-based modeling language and library developed specifically for system-level design.<ref name="SystemC_Standard">{{cite web |url=https://www.accellera.org/downloads/standards/systemc |title=SystemC Standards |publisher=Accellera Systems Initiative |access-date=2024-01-15}}</ref> The [[Open SystemC Initiative]] (OSCI), now part of [[Accellera]], has developed standardized TLM libraries that provide common interfaces and methodologies for transaction-level communication. However, the application of transaction-level modeling is not specific to the SystemC language and can be used with other languages. The concept of TLM first appears in the system-level language and modeling ___domain.<ref>L. Cai, D. Gajski, Transaction Level Modeling: An Overview, in proceedings of the Int. Conference on HW/SW Codesign and System Synthesis (CODES-ISSS), Oct. 2003, pp. 19–24</ref>

The methodology has become essential in modern [[electronic design automation]] (EDA) flows, particularly for creating [[virtual platform]]s that enable early [[software development]] and system validation before hardware implementation is complete.<ref name="Virtual_Platforms">{{cite conference |title=Virtual Platforms in System-Level Design |author=Schirner, Gunar |conference=Design Automation Conference |year=2013 |pages=804-809804–809 |doi=10.1145/2463209.2488885|doi-broken-date=1 July 2025 }}</ref> TLM models serve as executable specifications that bridge the gap between high-level system requirements and detailed hardware implementations. TLMs are used for [[high-level synthesis]] of [[register-transfer level]] (RTL) models for a lower-level modelling and implementation of system components. RTL is usually represented by a [[hardware description language]] source code (e.g. [[VHDL]], [[SystemC]], [[Verilog]]).{{r|TVLSIHB-2007|pp=1955-1957}}

==Background and history==

===Early development (1990s-2000s)===

Transaction-level modeling emerged in the late 1990s and early 2000s as a direct response to the increasing complexity of [[System-on-a-chip|system-on-chip]] designs and the limitations of traditional [[Register-transfer level|register-transfer level]] (RTL) modeling for system-level verification and software development.<ref name="Gajski_ESL">{{cite book |title=SpecC: Specification Language and Methodology |author=Gajski, Daniel D. |publisher=Kluwer Academic Publishers |year=2000 |isbn=978-0-7923-7822-5}}</ref> The semiconductor industry was experiencing a widening disparity between design complexity and designer productivity.<ref name="ITRS_Design">{{cite report |title=International Technology Roadmap for Semiconductors: Design |publisher=Semiconductor Industry Association |year=1999 |url=http://www.itrs.net/}}</ref>

The foundational concepts of TLM were developed simultaneously by several research groups and companies. [[Cadence Design Systems]] introduced early transaction-level concepts in their [[SpecC]] language in the mid-1990s,<ref name="SpecC_Origins">{{cite conference |title=SpecC: A Design Language for System Level Design |author=Gajski, Daniel D. |conference=Design Automation Conference |year=1997 |pages=464-469464–469 |doi=10.1145/266021.266138|doi-broken-date=1 July 2025 }}</ref> while [[Synopsys]] developed similar concepts in their [[SystemC]] methodology starting in 1999.<ref name="SystemC_History">{{cite journal |title=SystemC: Past, Present, and Future |author=Grötker, Thorsten |journal=IEEE Design & Test |volume=20 |issue=6 |pages=72-7772–77 |year=2003 |doi=10.1109/MDT.2003.1246169}}</ref>

In 2000, Thorsten Grötker, R&D manager at [[Synopsys]] was preparing a presentation on the communication mechanism in what was to become the [[SystemC]] 2.0 standard, and referred to it as "transaction-based modeling". Gilles Baillieu, then a corporate application engineer at Synopsys, insisted that the new term had to contain "level", as in "[[register-transfer level]]" or "behavioral level". The fact that TLM does not denote a single level of abstraction but rather a modeling technique didn't make him change his mind. It had to be "level" in order to make it stick. So it became "TLM".{{Citation needed|date=March 2008}}

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* Basic timing annotations

The TLM-1.0 standard was primarily focused on functional modeling and provided limited support for detailed timing analysis.<ref name="Ghenassia_TLM_1">{{cite book |title=Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems |editor=Ghenassia, Frank |publisher=Springer |year=2005 |chapter=TLM-1.0 Standard |pages=87-12487–124 |isbn=978-0-387-26233-4}}</ref>

===TLM 2.0 evolution and IEEE standardization (2008-2011)===

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* Multiple timing models (untimed, loosely timed, approximately timed)

* Standardized socket interfaces for interoperability

* Enhanced debugging and analysis capabilities<ref name="Aynsley_TLM2">{{cite book |title=ASIC and FPGA Verification: A Guide to Component Modeling |author=Aynsley, John |publisher=Springer |year=2009 |chapter=TLM-2.0 Reference |pages=145-198145–198 |isbn=978-1-4419-0564-5}}</ref>

TLM-2.0 was subsequently incorporated into the [[IEEE]] 1666-2011 standard for SystemC, providing official recognition and broader industry acceptance.<ref name="IEEE_1666_2011IEEE_TLM_Standard">{{cite standard |title=IEEE Standard for Standard SystemC Language Reference Manual |standard=IEEE Std 1666-2011 |publisher=IEEE |year=2012 |doi=10.1109/IEEESTD.2012.6134619}}</ref>

===Industry adoption and commercial tools===

By the mid-2000s, major [[Electronicelectronic Designdesign Automation|EDAautomation]] companies began incorporating TLM support into their commercial tools. [[Mentor Graphics]] (now [[Siemens EDA]]) introduced TLM support in their ModelSim simulator in 2004,<ref name="ModelSim_TLM">{{cite news |title=Mentor Graphics Adds SystemC TLM to ModelSim |newspaper=EE Times |date=2004-03-15}}</ref> followed by [[Cadence Design Systems]] with their Incisive platform in 2005.<ref name="Cadence_TLM">{{cite press release |title=Cadence Introduces Transaction-Level Modeling Flow |publisher=Cadence Design Systems |date=2005-09-12}}</ref>

Virtual platform companies such as [[CoWare]] (acquired by Synopsys in 2010),<ref name="Synopsys_CoWare">{{cite news |title=Synopsys Acquires CoWare for Virtual Prototyping |newspaper=EE Times |date=2010-02-22}}</ref> Vast Systems (acquired by Synopsys in 2007), and VaST Systems Technology contributed significantly to TLM's commercial adoption by providing high-performance virtual platforms based on TLM methodology.<ref name="Virtual_Platform_Market">{{cite report |title=Virtual Prototyping Market Analysis |publisher=Gary Smith EDA |year=2010}}</ref>

===Modern developments (2010s-present)===

The 2010s saw TLM become standard practice in the semiconductor industry, particularly for [[ARM architecture|ARM]]-based SoC design. [[ARM Holdings]] released comprehensive TLM models of their processor architectures, including [[ARM Cortex-A]] and [[ARM Cortex-M]] series processors.<ref name="ARM_TLM_Models">{{cite white paper |title=ARM Fast Models: System-Level Modeling for Software Development |publisher=ARM Holdings |year=2012}}</ref>

The rise of [[artificial intelligence]] and [[machine learning]] accelerators in the late 2010s created new demands for TLM modeling, leading to specialized libraries and methodologies for modeling [[neural processing unit]]s and other AI hardware.<ref name="AI_TLM">{{cite conference |title=Transaction-Level Modeling for AI Accelerator Design |author=Chen, Li |conference=Design Automation Conference |year=2019 |pages=1-61–6 |doi=10.1145/3316781.3317788|doi-broken-date=1 July 2025 }}</ref>

In 2020, OSCI merged with [[Accellera]], consolidating SystemC and TLM development under a single organization and ensuring continued evolution of the standards.<ref name="Accellera_OSCI_Merger">{{cite press release |title=Accellera and OSCI Merge to Advance System-Level Design Standards |publisher=Accellera Systems Initiative |date=2020-01-15}}</ref>

==Key Concepts==

{{Empty section|date=June 2025}}

==See also==

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*[https://systemc.org/ SystemC.org] - SystemC home page.

{{Digital electronics}}

[[Category:Electronic design automation]]