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Make usage of higher/lower cache levels consistent. L1 is the highest-level cache (as is correctly described in the rest of the article). |
→Recent implementation models: copyediting. |
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=== Intel i5 Raptor Lake-HX (2024) ===
6-core (performance | efficiency):
* L1 cache – 128 {{abbr|KB|kilobytes}} per core
* L2 cache – 2 {{abbr|MB|megabytes}} per core | 4–8 {{abbr|MB|megabytes}} semi-shared
* L3 cache – 20–24 {{abbr|MB|megabytes}} shared
=== AMD EPYC 9684X (Zen 4, 2023) ===
96-core:
* L1 cache – 64 {{abbr|KB|kilobytes}} per core
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* L3 cache – 96 {{abbr|MB|megabytes}} shared
=== AMD
6- to 16-core:
* L1 cache – 64 {{abbr|KB|kilobytes}} per core
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* L3 cache – 32 to 128 {{abbr|MB|megabytes}} shared
=== AMD Zen 2
* L1 cache – 32 KB data & 32 KB instruction per core, 8-way
* L2 cache – 512 KB per core, 8-way inclusive
* L3 cache – 16 MB local per 4-core CCX, 2 CCXs per chiplet, 16-way non-inclusive. Up to 64 MB on desktop CPUs and 256 MB on server CPUs
=== AMD Zen
* L1 cache – 32 KB data & 64 KB instruction per core, 4-way
* L2 cache – 512 KB per core, 4-way inclusive
* L3 cache – 4 MB local & remote per 4-core CCX, 2 CCXs per chiplet, 16-way non-inclusive. Up to 16 MB on desktop CPUs and 64 MB on server CPUs
=== Intel Kaby Lake
* L1 cache (instruction and data) – 64 KB per core
* L2 cache – 256 KB per core
* L3 cache – 2 MB to 8 MB shared<ref name=":3">{{Cite web|url=https://ark.intel.com/|title=Intel Kaby Lake Microrchitecture}}</ref>
=== Intel Broadwell
* L1 cache (instruction and data) – 64 {{abbr|KB|kilobytes}} per core
* L2 cache – 256 KK per core
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== See also ==
* CPU microarchitectures mentioned in this article:
** [[POWER7]]
** [[Broadwell (microarchitecture)|Intel Broadwell
** [[Zen (microarchitecture)|AMD Zen]]
** [[Apple silicon|Apple Silicon]]
* [[CPU cache]]
* [[Memory hierarchy]]
* [[CAS latency|CAS latency (RAM)]]
* [[Cache (computing)]]
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