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{{Short description|Data transfer channel connecting parts of a computer}}
{{About|buses in computer hardware|buses in software|Software bus}}
{{Use American English|date=March 2016}}
{{Use dmy dates|date=May 2020|cs1-dates=y}}
[[File:PCIExpress.jpg|250px|thumb|Four [[PCI Express]] bus card slots (from top to second from bottom: ×4, ×16, ×1 and ×16), compared to a 32-bit [[conventional PCI]] bus card slot (very bottom)]]
In [[computer architecture]], a '''bus''' (historically also called a '''data highway'''<ref name="Hollingdale_1958">{{cite conference |conference=Applications of Computers, University of Nottingham 15–19 September 1958 |title=Session 14. Data Processing |author-first=Stuart H. |author-last=Hollingdale |date=1958-09-19 |url=https://www.chilton-computing.org.uk/acl/literature/othermanuals/nottingham/p014.htm}}</ref> or '''databus''') is a communication system that transfers [[Data (computing)|data]] between components inside a [[computer]] or between computers.<ref>{{cite book |url=https://books.google.com/books?id=YVi8HVN-APwC&q=computer+buss+-sam&pg=PA27 |title=What Every Engineer Should Know about Data Communications |first=Carl |last=Clifton |publisher=CRC Press |date=September 19, 1986 |page=27 |isbn=9780824775667 |quote=The internal computer bus is a parallel transmission scheme; within the computer.... |url-status=live |archive-url=https://web.archive.org/web/20180117151300/https://books.google.com/books?id=YVi8HVN-APwC&lpg=PA27&dq=computer%20buss%20-sam&pg=PA27#v=onepage&q=computer%20buss%20-sam&f=false |archive-date=January 17, 2018}}</ref> It encompasses both [[Computer hardware|hardware]] (e.g., wires, [[optical fiber]]) and [[software]], including [[communication
Buses are categorized based on their role, such as [[system
Modern buses utilize both [[parallel communication|parallel]] and [[serial communication
==Address bus==
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However, this distinction{{mdashb}}that power is provided by the bus{{mdashb}}is not the case in many [[avionics|avionic systems]], where data connections such as [[ARINC 429]], [[ARINC 629]], [[MIL-STD-1553B]] (STANAG 3838), and EFABus ([[STANAG 3910]]) are commonly referred to as ''data buses'' or, sometimes, ''databuses''. Such [[avionics#Aircraft networks|avionic data buses]] are usually characterized by having several [[Line-replaceable unit|Line Replaceable Items/Units]] (LRI/LRUs) connected to a common, shared [[Media (communication)|media]]. They may, as with ARINC 429, be [[Simplex communication|simplex]], i.e. have a single source LRI/LRU or, as with ARINC 629, MIL-STD-1553B, and STANAG 3910, be [[Duplex (telecommunications)|duplex]], allow all the connected LRI/LRUs to act, at different times ([[half duplex]]), as transmitters and receivers of data.<ref name="ASSC 2003">Avionic Systems Standardisation Committee, ''Guide to Digital Interface Standards For Military Avionic Applications'', ASSC/110/6/2, Issue 2, September 2003</ref>
The frequency or the speed of a bus is measured in Hz such as MHz and determines how many clock cycles there are per second; there can be one or more data transfers per clock cycle. If there is a single transfer per clock cycle it is known as [[Single Data Rate]] (SDR), and if there are two transfers per clock cycle it is known as [[Double Data Rate]] (DDR) although the use of signalling other than SDR is uncommon outside of RAM. An example of this is PCIe which uses SDR.<ref>{{cite book | url=https://books.google.com/books?id=M_TKDwAAQBAJ&dq=pcie+rate&pg=PA155 | isbn=978-0-7384-5812-0 | title=IBM z15 (8561) Technical Guide | date=13 July 2022 | publisher=IBM Redbooks }}</ref> Within each data transfer there can be multiple bits of data. This is described as the width of a bus which is the number of bits the bus can transfer per clock cycle and can be synonymous with the number of physical electrical conductors the bus has if each conductor transfers one bit at a time.<ref>{{cite book | url=https://books.google.com/books?id=hDwDEAAAQBAJ&dq=bus+width&pg=PA54 | isbn=978-1-000-11716-5 | title=Foundations of Computer Technology | date=25 October 2020 | publisher=CRC Press }}</ref><ref>{{cite book | url=https://books.google.com/books?id=j0wsBgAAQBAJ&dq=computer+bus+frequency&pg=PA39 | title=PC Systems, Installation and Maintenance | isbn=978-1-136-37442-5 | last1=Beales | first1=R. P. | date=11 August 2006 | publisher=Routledge }}</ref><ref>{{cite web | url=https://computer.howstuffworks.com/motherboard4.htm#:~:text=Bus%20speed%20usually%20refers%20to,dramatically%20affect%20a%20computer%27s%20performance | title=How Motherboards Work | date=20 July 2005 }}</ref> The data rate in bits per second can be obtained by multiplying the number of bits per clock cycle times the frequency times the number of transfers per clock cycle.<ref>{{cite book | url=https://books.google.com/books?id=6FnMBQAAQBAJ&q=Data+rate&pg=PA92 | title=Computer Busses | isbn=978-1-4200-4168-2 | last1=Buchanan | first1=Bill | date=25 April 2000 | publisher=CRC Press }}</ref><ref>{{cite book | url=https://books.google.com/books?id=vpnJDwAAQBAJ&q=Width | title=The Computer Engineering Handbook | isbn=978-1-4398-3316-2 | last1=Oklobdzija | first1=Vojin G. | date=5 July 2019 | publisher=CRC Press }}</ref> Alternatively a bus such as [[PCIe]] can use modulation or encoding such as [[PAM4]]<ref>{{Cite web |last=Robinson |first=Dan |date=2022-01-12 |title=Final PCIe 6.0 specs unleashed: 64 GTps link speed incoming... with products to follow in 2023 |url=https://www.theregister.com/2022/01/12/final_pcie_60_specs_released/ |website=www.theregister.com}}</ref><ref>{{cite web | url=https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | archive-url=https://web.archive.org/web/20240404125350/https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | url-status=dead | archive-date=4 April 2024 | title=PCIe 7.0 Draft 0.5 Spec Available: 512 GB/S over PCIe x16 on Track for 2025 }}</ref><ref>{{cite web | url=https://arstechnica.com/gadgets/2022/01/pci-express-6-0-spec-is-finalized-doubling-bandwidth-for-ssds-gpus-and-more/ | title=PCIe 5.0 is just beginning to come to new PCS, but version 6.0 is already here | date=12 January 2022 }}</ref> which groups 2 bits into symbols which are then transferred instead of the bits themselves, and allows for an increase in data transfer speed without increasing the frequency of the bus. The effective or real data transfer speed/rate may be lower due to the use of encoding that also allows for error correction such as 128/130b (b for bit) encoding.<ref>{{cite web | url=https://www.xda-developers.com/pcie-6/ | title=PCIe 6.0: Everything you need to know about the upcoming standard | date=30 June 2024 }}</ref><ref>{{cite web | url=https://semiengineering.com/knowledge_centers/communications-io/off-chip-communications/pam-4-signaling/ | title=PAM-4 Signaling }}</ref><ref>{{cite book | url=https://books.google.com/books?id=M_TKDwAAQBAJ&dq=pcie+rate&pg=PA155 | isbn=978-0-7384-5812-0 | title=IBM z15 (8561) Technical Guide | date=13 July 2022 | publisher=IBM Redbooks }}</ref> The data transfer speed is also known as the bandwidth.<ref>{{cite book | url=https://books.google.com/books?id=eV1_LjW3pTkC&dq=agp+2133&pg=PA304 | isbn=978-0-7897-2745-9 | title=Upgrading and Repairing PCS | date=2003 | publisher=Que }}</ref><ref>{{cite web | url=https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | archive-url=https://web.archive.org/web/20240404125350/https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | url-status=dead | archive-date=4 April 2024 | title=PCIe 7.0 Draft 0.5 Spec Available: 512 GB/S over PCIe x16 on Track for 2025 }}</ref>
=== Bus multiplexing ===
{{main | Bus encoding#Other examples of bus encoding }}
The simplest [[system bus]] has completely separate input data lines, output data lines, and address lines.
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Early [[computer]] buses were bundles of wire that attached [[computer memory]] and peripherals. Anecdotally termed the ''digit trunk'' in the early Australian [[CSIRAC]] computer,<ref>{{cite book|last1=McCann|first1=Doug|last2=Thorne|first2=Peter|title=The Last of The First, CSIRAC: Australias First Computer|pages=8–11, 13, 91|publisher=University of Melbourne Computing Science|year=2000|url=https://cis.unimelb.edu.au/about/csirac/last-of-the-first|isbn=0-7340-2024-4}}</ref> they were named after electrical power buses, or [[busbar]]s. Almost always, there was one bus for memory, and one or more separate buses for peripherals. These were accessed by separate instructions, with completely different timings and protocols.
One of the first complications was the use of [[interrupt]]s. Early computer programs performed [[I/O]] by [[Busy waiting|waiting in a loop]] for the peripheral to become ready. This was a waste of time for programs that had other tasks to do. Also, if the program attempted to perform those other tasks, it might take too long for the program to check again, resulting in loss of data. Engineers thus arranged for the peripherals to interrupt the [[CPU]]. The interrupts had to be prioritized, because the CPU can only execute code for one peripheral at a time, and some devices are more time-critical than others.
High-end systems introduced the idea of [[channel controller]]s, which were essentially small computers dedicated to handling the input and output of a given bus. [[IBM]] introduced these on the [[IBM 709]] in 1958, and they became a common feature of their platforms. Other high-performance vendors like [[Control Data Corporation]] implemented similar designs. Generally, the channel controllers would do their best to run all of the bus operations internally, moving data when the CPU was known to be busy elsewhere if possible, and only using interrupts when necessary. This greatly reduced CPU load, and provided better overall system performance.
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[[Digital Equipment Corporation]] (DEC) further reduced cost for mass-produced [[minicomputer]]s, and [[Memory-mapped I/O|mapped peripherals]] into the memory bus, so that the input and output devices appeared to be memory locations. This was implemented in the [[Unibus]] of the [[PDP-11]] around 1969.<ref>{{cite conference |title= A New Architecture for Mini-Computers—The DEC PDP-11 |author1= C. Gordon Bell |author2= R. Cady |author3= H. McFarland |author4= B. Delagi |author5= J. O'Laughlin |author6= R. Noonan |author7= W. Wulf |conference= Spring Joint Computer Conference |pages= 657–675 |year= 1970 |url= http://research.microsoft.com/en-us/um/people/gbell/CGB%20Files/New%20Architecture%20PDP11%20SJCC%201970%20c.pdf |url-status= live |archive-url= https://web.archive.org/web/20111127001221/http://research.microsoft.com/en-us/um/people/gbell/CGB%20Files/New%20Architecture%20PDP11%20SJCC%201970%20c.pdf |archive-date= 2011-11-27 }}</ref>
Early [[microcomputer]] bus systems were essentially a passive [[backplane]] connected directly or through buffer amplifiers to the pins of the
For instance, a [[disk drive]] controller would signal the CPU that new data was ready to be read, at which point the CPU would move the data by reading the memory ___location that corresponded to the disk drive. Almost all early microcomputers were built in this fashion, starting with the [[S-100 bus]] in the [[Altair 8800]] computer system.
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Buses such as [[Wishbone (computer bus)|Wishbone]] have been developed by the [[open source hardware]] movement in an attempt to further remove legal and patent constraints from computer design.
The [[Compute Express Link]] (CXL) is an [[open standard]] [[interconnect]] for high-speed
==Examples of internal computer buses==
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