Content deleted Content added
KMaster888 (talk | contribs) ce |
|||
| (30 intermediate revisions by 21 users not shown) | |||
Line 1:
{{nofootnotes|date=June 2011}}
In [[ARM Limited|ARM]] [[ARM_architecture|processor architecture]], '''26-bit''' refers to the design used in the original ARM processors, where the [[Program Counter]]('''PC''') and [[Status_register|Processor Status Register]]('''PSR''') were combined into one 32-bit [[Processor_registers|register]] (R15), the Status flags filling the high 6 bits and the Program Counter taking up the lower "26" bits. ▼
{{Computer architecture bit widths}}
In [[computer architecture]], '''26-bit''' [[integers]], [[memory address|memory addresses]], or other [[Data (computing)|data]] units are those that are 26 bits wide, and thus can represent unsigned values up to 67,108,863. Two examples of computer processors that featured 26-bit memory addressing are certain second generation IBM [[System/370]] [[mainframe computer]] models introduced in 1981 (and several subsequent models), which had 26-bit physical addresses but had only the same 24-bit virtual addresses as earlier models, and the first generations of [[ARM Limited|ARM]] processors.
This design enabled more efficient [[Computer_program|program]] execution, as the Program Counter and Status flags could be saved and restored with a single operation. This resulted in faster [[subroutine]] calls and [[interrupt]] response than traditional designs, which would have to do two register load/saves when calling or returning from a subroutine.▼
== History ==
=== IBM System/370 ===
As [[data processing]] needs continued to grow, IBM and their customers faced challenges directly addressing larger memory sizes. In what ended up being a short-term "emergency" solution, a pair of IBM's second wave of System/370 models, the 3033 and 3081, introduced 26-bit real memory addressing, increasing the System/370's amount of physical memory that could be attached by a factor of 4 from the previous [[24-bit computing|24-bit]] limit of 16 MB. IBM referred to 26-bit addressing as "extended real addressing," and some subsequent models also included 26-bit support. However, only 2 years later, IBM introduced [[31-bit computing|31-bit]] memory addressing, expanding both physical and virtual addresses to 31 bits, with its System/370-XA models, and even the popular 3081 was upgradeable to XA standard.
Given 26-bit's brief history as the state-of-the-art in memory addressing available in IBM's model range, and given that virtual addresses were still limited to 24 bits, [[software]] exploitation of 26-bit mode was limited. The few customers that exploited 26-bit mode eventually adjusted their applications to support 31-bit addressing,{{cn|date=March 2014}} and IBM dropped support for 26-bit mode after several years producing models supporting 24-bit, 26-bit, and 31-bit modes. The 26-bit mode is the only addressing mode that IBM removed from its line of mainframe computers descended from the [[System/360]]. All the other addressing modes, including now 64-bit mode, are supported in current model mainframes.
Despite being [[32-bit]] internally, processors prior to the ARM6 had only a '''26-bit PC and [[address bus]]''', and were consequently limited to 64MB of addressable [[Random_Access_Memory|memory]]. This was still a vast amount of memory at the time, but because of this limitation, architectures since have included various steps away from the original 26-bit design.▼
=== Early ARM processors ===
The ARM6 introduced a '''32-bit PC''' and '''separate PSR''', as well as a '''32-bit address bus''', allowing 4GB of memory to be addressed. The change in the PC/PSR layout caused incompatibility with code written for previous architectures, so the processor also included a 26-bit compatibility mode which used the old PC/PSR combination. The processor could still address 4GB in this mode, but could not [[Execution_(computers)|execute]] anything above address 3FFFFFC (64MB). This mode was used by [[RISC OS]] running on the [[Risc_PC|Acorn Risc PC]] to utilise the new processors while retaining compatibility with existing software.▼
▲In the [[
In fact, because the program counter is always word-aligned the lowest two bits are always zero which allowed the designers to reuse these two bits to hold the processor's mode bits too. The four modes allowed were USR26, SVC26, IRQ26, FIQ26; contrast this with the 32 possible modes available when the program status was separated from the program counter in more recent [[ARM architecture]]s.
▲This design enabled more efficient [[
==External links==▼
*[http://rtds.cs.tamu.edu/web_462/techdocs/ARM/appsnotes/Apps11vC.html Differences Between ARM6 and Earlier ARM Processors]▼
▲Despite
*[http://www.iyonix.com/32bit/download/32bit_dev.pdf "Using the Acorn C/C++ Development Environment to write 32-bit RISC OS software"] - Details on the architectural changes and converting code between 26- and 32-bit.▼
▲The
ARM architecture version 4 made the support of the 26-bit addressing modes optional, and ARM architecture version 5 onwards has removed them entirely.
▲== External links ==
▲* [
▲* [https://web.archive.org/web/20050406022001/http://www.iyonix.com/32bit/download/32bit_dev.pdf "Using the Acorn C/C++ Development Environment to write 32-bit RISC OS software"] - Details on the architectural changes and converting code between 26-bit and 32-bit.
* http://www.heyrick.co.uk/assembler/32bit.html - Information on converting assembler to 32-bit
| |||