POWER4: Difference between revisions

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{{Short description|2001 family of microprocessors by IBM}}

{{cleanup-date|June 2005}}

{{Infobox CPU

| name = POWER4

| image = POWER4-SCM.jpg

| caption = POWER4 SCM

| produced-start = 2001

| produced-end =

| slowest = 1.1 | slow-unit = GHz

| fastest = 1.9 | fast-unit = GHz

| size-from = 180 nm

| size-to = 130 nm

| designfirm = IBM

| arch = [[PowerPC]] (PowerPC v.2.00/01)

| microarch =

| numcores = 2

| l1cache = 64+32 kB/core

| l2cache = 1.41 MB/chip

| l3cache = 32 MB off chip

| predecessor = [[POWER3]], [[RS64]]

| successor = [[POWER5]]

| application =

}}

{{POWER, PowerPC, and Power ISA}}

The '''POWER4''' is a [[microprocessor]] developed by [[IBM|International Business Machines]] (IBM) that implemented the [[64-bit]] [[PowerPC]] and PowerPC AS [[instruction set architecture]]s. Released in 2001, the POWER4 succeeded the [[POWER3]] and [[RS64]] microprocessors, enabling [[RS/6000]] and [[IBM AS/400|eServer iSeries models of AS/400]] computer servers to run on the same processor, as a step toward converging the two lines. The POWER4 was a [[Multi-core processor|multicore]] microprocessor, with two cores on a single die, the first non-embedded microprocessor to do so.<ref>{{cite web|url=http://www.cpushack.com/2011/01/24/ibms-server-processors-the-rs64-and-the-power|title=IBM's Server Processors: The RS64 and the POWER|work=The CPU Shack Museum|date=2011-01-24|access-date=2015-04-17}}</ref> POWER4 Chip was first commercially available multiprocessor chip.<ref name="stallings">William Stallings, ''Computer Organization and Architecture'', Seventh Edition, -pp 44</ref> The original POWER4 had a clock speed of 1.1 and 1.3&nbsp;GHz, while an enhanced version, the POWER4+, reached a clock speed of 1.9&nbsp;GHz. The [[PowerPC 970]] is a derivative of the POWER4.

==Functional Layoutlayout==

[[Image:POWER4plus.jpg|thumb|95px|right|IBM POWER4+]]

[[Image:Power4 core schema.png|thumb|right|The logic schema of the POWER4 core]]

[[Image:Power4 chip schema.png|thumb|right|The logic schema of the POWER4 processor]]

The functionalPOWER4 unithas ofa the POWER4™ consists of two 64-bit implementations of the PowerPC AS Architecture. Anunified L2 unified cache which is, divided into three equal parts. each havingEach has itits own independent L2 controller which can feed 32 bytes of data per cycle.{{Clarify|date=June 2009}} The Core Interface Unit (CIU) which connects each L2 controller to either the (data cache/ or instruction cache) in either of the two processors. AThe NonCacheableNon-Cacheable (NC) Unit is devoted to each processor which is responsible for handling instruction serializing functions and performing any noncacheable operations in the storage topalogytopology. AnThere is an L3 cache controlercontroller, and the directory of the L3 (but the actual memory is off-chip). AThe GX bus controller which controllescontrols I/O device communications, and there are two 4-byte wide GX buses, one for Incomingincoming and the other for Outgoingoutgoing. AThe Fabric Controller which is the master controller for the network of buses, controlling communications for both L1/L2 controllers, communications between POWER4™POWER4 chips {4-way, 8-way, 16-way, 32-way} and POWER4™POWER4 MCM’sMCM's. Trace-and-Debug, (used for First Failure Data Capture), is provided. A There is also a Built In Self Test function (BIST). and Performance Monitoring Unit (PMU). [[Power-Onon Resetreset]] (POR) is supported.

===Execution Unitunits===

The '''POWER4''' chip is a computer processor based on the [[IBM POWER]] processor architecture. Released in [[2001]], the POWER4 chip is based on the previous [[POWER3]] chip design, and includes compatibility with the [[PowerPC]]. The POWER4 chip is a [[multicore]] chip, including two PowerPC cores.

The Power4POWER4 implements a [[superscalar]] [[microarchitecture]] through high-frequency [[Speculative execution|speculative]] [[out-of-order execution]] using 8eight independent execution units. The 8They are: 2two floating-point units (FP1-2), 2two load-store units units(LD1-2), 2two fixed-point units (FX1-2), 1a branch unit (BR), and 1a conditional-register unit (CR). These execution units can complete up to eight operations per clock (not including the BR and CR units):

*each floating point unit can complete one [[fused multiply–add]] per clock (two operations),

==Functional Layout==

*each load–store unit can complete one instruction per clock,

[[Image:power4blockdiagram.jpg|thumb|400px|right|IBM POWER4 Block Diagram]]

*each fixed-point unit can complete one instruction per clock.

The functional unit of the POWER4™ consists of two 64-bit implementations of the PowerPC AS Architecture. An L2 unified cache which is divided into three equal parts each having it own independent L2 controller which can feed 32 bytes of data per cycle. The Core Interface Unit (CIU) which connects each L2 controller to either the (data cache/instruction cache) in either of the two processors. A NonCacheable (NC) Unit is devoted to each processor which is responsible for handling instruction serializing functions and performing any noncacheable operations in the storage topalogy. An L3 cache controler, and the directory of the L3 (but the actual memory is off-chip). A GX bus controller which controlles I/O device communications, and two 4-byte wide GX buses one for Incoming and the other for Outgoing. A Fabric Controller which is the master controller for the network of buses, controlling communications for both L1/L2 controllers, communications between POWER4™ chips {4-way, 8-way, 16-way, 32-way} and POWER4™ MCM’s. Trace-and-Debug (used for First Failure Data Capture). A Built In Self Test function (BIST). Performance Monitoring Unit (PMU). Power-On Reset (POR).

The pipeline stages are:

===Execution Unit===

[[Image:POWER4executionunitdiagram.jpg|thumb|250px|left|POWER4 Execution Unit]]

The Power4 implements a superscalar microarchitecture through high-frequency speculative out-of-order execution using 8 independent execution units. The 8 are: 2 floating-point units(FP1-2), 2 load-store units(LD1-2), 2 fixed-point units(FX1-2), 1 branch unit(BR), and 1 conditional-register unit(CR).

*Branch Prediction

*Instruction Fetch

*Decode, Crack and Group Formation

*Group Dispatch and Instruction Issue

*Load/StoreLoad–Store Unit Operation

*Load/Store Unit Operation

**Load Hit Store

**Store Hit Load

**Load Hit Load

*Instruction Execution Pipeline

==Multi-chip configuration==

<!--

==Memory Maping==

The POWER4 also came in a configuration using a [[multi-chip module]] (MCM) containing four POWER4 dies in a single package, with up to 128 MB of shared L3 ECC cache per MCM.

==Memory CachLayout==

-->

==Multi-Chip Configuration==

[[Image:POWER4multichipmodule.jpg|thumb|100px|right|IBM POWER4 MCM]]

Not only did the POWER4 become the first microprocessor to incorporate Dual-cores in a single die, but it also concurrently became the first to implement a Multi-Chip-Module(MCM) which contains four POWER4 Microprocessors in a single package.

==Parametrics==

{| class="wikitable"

|+POWER4 18nm180&nbsp;nm@CMOS 8S3 SOI

{| border="1" cellpadding="2"

|+POWER4 18nm@CMOS 8S3 SOI

|-

! Clock GHz !! >1.3&nbsp;GHz || ||

|-

! Power

| 115 W || 1.5 V @ 1.1 &nbsp;GHz ||

|-

! Transistors|
|

| 174 million||

|-

! Gate L

| 90 &nbsp;nm|| ||

|-

! Gate oxide|
|

| 2.3 &nbsp;nm||

|-

! Metal-layer

|! pitch|| thickness ||

|-

! M1

! M1|| 500 &nbsp;nm || 310 &nbsp;nm ||

|-

! M2

! M2 || 630 &nbsp;nm || 310 &nbsp;nm||

|-

! M3-M5 || 630 nm || 420 nm ||

| 630&nbsp;nm || 20&nbsp;nm

|-

! M6(MQ) |
| 1260 &nbsp;nm || 920 &nbsp;nm ||

|-

! M7(LM) |
| 1260 &nbsp;nm || 920 &nbsp;nm ||

|-

! Dielectric |
| ~4.2|| ||

|-

! Vdd |
| 1.6 V || ||

|}

== POWER4+ ==

[[File:POWER4+-SCM.jpg|thumb|POWER4+ SCM]]

The POWER4+, released in 2003, was an improved version of the POWER4 that ran at up to 1.9&nbsp;GHz.<ref>{{cite web|title=IBM POWER Roadmap|url=http://speleotrove.com/decimal/IBM-Power-Roadmap-McCredie.pdf|website=Speleotrove|publisher=IBM|access-date=6 March 2018|page=2|date=2006}}</ref> It contained 184 million transistors, measured 267&nbsp;mm², and was fabricated in a 0.13&nbsp;μm SOI CMOS process with eight layers of copper interconnect.

== See also ==

*[[PowerPC 970]]

*[[IBM POWER Architecture]]

*[[IBM Power microprocessors]]

==Notes==

{{Reflist}}

== References ==

*[[Microprocessor Report"Power4 Focuses on Memory Bandwidth". (magazine6 October 1999)|. ''[[Microprocessor Report]]''.

* "IBM's Power4 Unveiling Continues". (20 November 2000). ''[[Microprocessor Report]]''.

*{{cite web|url=http://www.cc.gatech.edu/~bader/COURSES/UNM/ece637-Fall2003/papers/TDF02.pdf|title=POWER4 System Microarchitecture|access-date=2012-06-07|publisher=IBM|archive-url=https://web.archive.org/web/20131107140531/http://www.cc.gatech.edu/~bader/COURSES/UNM/ece637-Fall2003/papers/TDF02.pdf|archive-date=2013-11-07|url-status=dead}}

*{{cite journal|author1=J. M. Tendler |author2=J. S. Dodson |author3=J. S. Fields, Jr. |author4=H. Le |author5=B. Sinharoy |name-list-style=amp |year=2002|title=POWER4 system microarchitecture|journal=IBM Journal of Research and Development|volume=46|issue=1|pages=5&ndash;26|doi=10.1147/rd.461.0005|url=http://www.research.ibm.com/journal/rd/461/tendler.html|access-date=2006-07-21|issn=0018-8646|url-access=subscription}}

*{{cite journal|author1=J. D. Warnock |author2=J. M. Keaty |author3=J. Petrovick |author4=J. G. Clabes |author5=C. J. Kircher |author6=B. L. Krauter |author7=P. J. Restle |author8=B. A. Zoric |author9=C. J. Anderson |name-list-style=amp |year=2002|title=The circuit and physical design of the POWER4 microprocessor|journal=IBM Journal of Research and Development|volume=46|issue=1|pages=27&ndash;52|doi=10.1147/rd.461.0027|url=http://www.research.ibm.com/journal/rd/461/warnock.html|access-date=2006-07-21|issn=0018-8646|url-access=subscription}}

{{DEFAULTSORT:Power4}}

[[Category:POWERIBM architecturemicroprocessors]]

[[Category:PowerPC microprocessors]]

[[Category:64-bit microprocessors]]