Application-specific instruction set processor: Difference between revisions

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{{Short description|Processor with an instruction set customized (optimized) for a specific task}}

An '''application-specific instruction-set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[Central processing unit|CPU]] and the performance of an [[ASIC]].

{{Use American English|date=March 2019}}

{{Use mdy dates|date = March 2019}}

{{More footnotes|date=January 2015}}

An '''application-specific instruction- set processor''' ('''ASIP''') is a component used in [[system- on- a- chip]] design. The [[instruction set architecture]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[Centralcentral processing unit|CPU]] (CPU) and the performance of an [[ASICapplication-specific integrated circuit]] (ASIC).

Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to ana [[FPGAfield-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite book|last1=Jain|first1=M.K.|last2=Balakrishnan|first2=M.|last3=Kumar|first3=A.|title=VLSI Design 2001. Fourteenth International Conference on VLSI Design |chapter=ASIP design methodologies: Survey and issues |date=2001|___location=Bangalore, India|publisher=IEEE Comput. Soc|pages=76–81|doi=10.1109/ICVD.2001.902643|isbn=978-0-7695-0831-3|s2cid=14053636 }}</ref>

ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014.</ref> or video coding.<ref>Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014</ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref>

== Literature ==

* {{cite book |title=Optimized ASIP Synthesis from Architecture Description Language Models |author=Oliver Schliebusch, Heinrich Meyr, Rainer Leupers |year=2007 |publisher=Springer |___location=Dordrecht |isbn=978-1-4020-5685-7 }}

* {{cite book |title=Customizable Embedded Processors |author=Paolo Ienne, Rainer Leupers (eds.) |year=2006 |publisher=Morgan Kaufmann |___location=San Mateo, CA |isbn=978-0-12-369526-0 }}

* {{cite book |title=Building ASIPs: The Mescal Methodology |author=Matthias Gries, Kurt Keutzer (eds.) |year=2005 |publisher=Springer |___location=New York |isbn=978-0-387-26057-0 }}

== Examples ==

{{CPU technologies}}

[[RISC-V|RISC-V Instruction Set Architecture]] (ISA) provides minimum base instruction sets that can be extended with additional application-specific instructions.<ref>{{Cite book |last=Krste |first=CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Waterman, Andrew Lee, Yunsup Patterson, David A Asanovi |title=The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0 |date=2014-05-06 |oclc=913589579}}</ref> The base instruction sets provide simplified control flow, memory and arithmetic operations on registers. Its modular design allows the base instructions to be extended for standard application-specific operations such as integer multiplication/division (M), single-precision floating point (F), or bit manipulation (B). For the non-standard instruction extensions, encoding space of the ISA is divided into three parts: ''standard, reserverd,'' and ''custom.'' The ''custom'' encoding space is used for vendor-specific extensions.

==See also==

[[Category:Instruction processing]]

* [[de:Application-specific instruction-setintegrated processorcircuit]]

* [[System on Chip]]

* [[Digital signal processor]]

==References==

[[Category:Gate arrays]]

{{reflist}}

[[Category:Integrated circuits]]

== Literature ==

{{Computer-hardware-stub}}

* {{cite book |title=Embedded DSP Processor Design: Application Specific Instruction Set Processors |author=Dake Liu |year=2008 |publisher=Elsevier Mogan Kaufmann |___location=MA |isbn=978-0-12-374123-3 }}

* {{cite book |title=Optimized ASIP Synthesis from Architecture Description Language Models |authorauthor1=Oliver Schliebusch, |author2=Heinrich Meyr, |author3=Rainer Leupers |year=2007 |publisher=Springer |___location=Dordrecht |isbn=978-1-4020-5685-7 }}

* {{cite book |title=Customizable Embedded Processors |author=Paolo Ienne, Rainer Leupers (eds.) |year=2006 |publisher=Morgan Kaufmann |___location=San Mateo, CA |editor-last2=Ienne |editor-first2=Paolo |isbn=978-0-12-369526-0 |editor-last=Leupers |editor-first=Rainer}}

* {{cite book |title=Building ASIPs: The Mescal Methodology |author=Matthias Gries, Kurt Keutzer (eds.) |year=2005 |publisher=Springer |___location=New York |editor-last2=Keutzer |editor-first2=Kurt |isbn=978-0-387-26057-0 |editor-last=Gries |editor-first=Matthias}}

==External links==

[[de:Application-specific instruction-set processor]]

*[http://tce.cs.tut.fi TTA-Based Codesign Environment (TCE), an open source (MIT licensed) toolset for design of application specific TTA processors.]

[[it:Application-specific instruction-set processor]]

[[ru:ASIP]]

{{CPU technologies}}

Increasing Design Costs

Designing an integrated circuit is getting increasingly expensive with each succeeding generation. Design difficulties arise from four distinct causes:

[[itCategory:Application-specific instruction-setintegrated processorcircuits]]

Deep-Submicron Effects (DSM):

[[Category:Coprocessors]]

The primary change is the increase in interconnect delay as a fraction of

[[Category:Gate arrays]]

the gate delay due to scaling effects. Since this is not available till physical design is over, the traditional synthesis flow of logic synthesis, with simple interconnect wire-load models, followed by physical synthesis does not work anymore.

[[Category:Instruction processing]]

[[Category:Integrated circuits]]

Increased Complexity: The flip-side of smaller geometries is that we can

now integrate more transistors on the same die. This is amplified by the fact that manufacturing advances have further increased possible die-sizes.

Heterogeneous Integration: Increased functionality of systems at lower costs requires the integration of heterogeneous functionality on the same die. In addition to the traditional digital part, it is not uncommon to integrate analog and mixed signal components on the same die.

Shrinking Time-to-Market: : While the above three factors arise out of technology challenges, the fourth arises from commercial challenges. Increasingly, the time-to-market for products is shrinking – providing the added degree of difficulty in realizing commercially successful designs.

Increasing Manufacturing Costs

Mask costs for designs in today’s 180-130nm technologies are in the 0.5-1M$ range.

Testing 100M-1B transistor circuits at high operating frequencies poses significant challenges.

ITRS 2001 states that “test costs have grown exponentially compared to manufacturing costs".