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{{Short description|State machines and generalizations in UML}}
{{Use American English|date = April 2019}}
{{For|a general introduction|State diagram}}
{{UML diagram types}}
'''UML state machine''',<ref name=
|chapter=StateMachines
| author = OMG▼
|series=[[Object Management Group |OMG]] Document Number formal/2017-12-05
| url = http://www.omg.org/spec/UML/2.2/Superstructure/PDF▼
|date=December 2017
|date=February 2009}}</ref> known also as '''UML statechart''', is an object-based variant of [[Harel statechart]]<ref name=Harel87>{{Cite web▼
|publisher=[[Object Management Group]] Standards Development Organization (OMG SDO)
|page=305
}}
</ref>
formerly known as '''UML statechart''', is an extension of the [[mathematics|mathematical]] concept of a [[Finite-state machine|finite automaton]] in [[computer science]] applications as expressed in the [[Unified Modeling Language]] (UML) notation.
The concepts behind it are about organizing the way a device, computer program, or other (often technical) process works such that an entity or each of its sub-entities is always in exactly one of a number of possible states and where there are well-defined conditional transitions between these states.
▲
| title = Statecharts: A Visual Formalism for Complex Systems
| author = Harel, David
| url = http://www.wisdom.weizmann.ac.il/~dharel/SCANNED.PAPERS/Statecharts.pdf
| date = 1987}}</ref> adapted and extended by the [[Unified Modeling Language]]. UML state machines overcome the main limitations of traditional [[finite state machines]] while retaining their main benefits. UML statecharts introduce the new concepts of [[#Hierarchically nested states|hierarchically nested states]] and [[#Orthogonal regions|orthogonal regions]], while extending the notion of [[#Actions and transitions|actions]]. UML state machines have the characteristics of both [[Mealy machine]]s and [[Moore machine]]s. They support [[#Actions and transitions|actions]] that depend on both the state of the system and the triggering [[#Events|event]], as in Mealy machines, as well as [[#Entry and exit actions|entry and exit actions]], which are associated with states rather than transitions, as in Moore machines.▼
adapted and extended by UML.<ref name=OMG/><ref name=Dru06>D. Drusinsky, [http://www.elsevier.com/wps/find/bookdescription.cws_home/707940/description#description ''Modelling and verification using UML statecharts''], [[Elsevier]], 2006</ref>
The goal of UML state machines is to overcome the main limitations of traditional [[finite-state machine]]s while retaining their main benefits.
▲
| title = A crash course in UML state machines
| url = http://www.embedded.com/design/prototyping-and-development/4008247/A-crash-course-in-UML-state-machines-Part-1
|date=March 2009}}</ref>
The term "UML state machine" can refer to two kinds of state machines: ''behavioral state machines'' and ''protocol state machines''.
Behavioral state machines can be used to model the behavior of individual entities (e.g., class instances) Protocol state machines are used to express usage protocols and can be used to specify the legal usage scenarios of classifiers, interfaces, and ports. == Basic state machine concepts ==
Many software systems are [[event-driven programming|event-driven]], which means that they continuously wait for the occurrence of some external or internal '''[[#Events|event]]''' such as a mouse click, a button press, a time tick, or an arrival of a data packet. After recognizing the event, such systems react by performing the appropriate computation that may include manipulating the hardware or generating “soft” events that trigger other internal software components. (
The response to an event generally depends on both the type of the event and on the internal '''[[#States|state]]''' of the system and can include a change of state leading to a '''[[#Actions and transitions|state transition]]'''. The pattern of events, states, and state transitions among those states can be abstracted and represented as a '''[[finite
The concept of
{{Cite book
| last1 = Samek
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| isbn = 978-0-7506-8706-5
| page = 728}}
</ref>
=== Basic UML state diagrams ===
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=== Events ===
An '''event''' is something that happens that affects the system.
In the most general terms, an '''event''' is an occurrence in time and space that has significance to the system. Strictly speaking, in the UML specification,<ref name=UML2_2></ref> the term event refers to the type of occurrence rather than to any concrete instance of that occurrence. For example, Keystroke is an event for the keyboard, but each press of a key is not an event but a concrete instance of the Keystroke event. Another event of interest for the keyboard might be Power-on, but turning the power on tomorrow at 10:05:36 will be just an instance of the Power-on event.▼
Strictly speaking, in the UML specification,<ref name=OMG/>
the term event refers to the type of occurrence rather than to any concrete instance of that occurrence.
▲
An event can have associated '''parameters''', allowing the event instance to convey not only the occurrence of some interesting incident but also quantitative information regarding that occurrence. For example, the Keystroke event generated by pressing a key on a computer keyboard has associated parameters that convey the character scan code as well as the status of the Shift, Ctrl, and Alt keys.
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=== States ===
=== Extended states ===
{{Cite book
| last1 = Selic
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</ref>
State machines supplemented with ''extended state'' variables are called '''extended state machines''' and UML state machines belong to this category. Extended state machines can apply the underlying formalism to much more complex problems than is practical without including extended state variables. For
[[Image:UML state machine Fig2.png|thumb|upright=3|center|Figure 2: Extended state machine of "cheap keyboard" with extended state variable key_count and various guard conditions]]
The state diagram from Figure 2 is an example of an extended state machine, in which the complete condition of the system (called the ''extended state'') is the combination of a qualitative aspect—the
The obvious advantage of extended state machines is flexibility. For example,
This flexibility of extended state machines comes with a price, however, because of the complex coupling between the "qualitative" and the "quantitative" aspects of the extended state. The coupling occurs through the guard conditions attached to transitions, as shown in Figure 2.
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'''Guard conditions''' (or simply guards) are [[Boolean function|Boolean expressions]] evaluated dynamically based on the value of [[#Extended states|extended state variables]] and [[#Events|event parameters]]. Guard conditions affect the behavior of a state machine by enabling actions or transitions only when they evaluate to TRUE and disabling them when they evaluate to FALSE. In the UML notation, guard conditions are shown in square brackets (e.g., <code>[key_count == 0]</code> in Figure 2).
The need for guards is the immediate consequence of adding memory [[#Extended states|extended state variables]] to the state machine formalism. Used sparingly, extended state variables and guards make up
On the other hand, it is possible to abuse extended states and guards quite easily.<ref name=Samek03d>{{Cite web
| title = Back to Basics
| author = Samek, Miro
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Switching from one state to another is called '''state transition''', and the event that causes it is called the triggering event, or simply the '''trigger'''. In the keyboard example, if the keyboard is in the "default" state when the CapsLock key is pressed, the keyboard will enter the "caps_locked" state. However, if the keyboard is already in the "caps_locked" state, pressing CapsLock will cause a different transition—from the "caps_locked" to the "default" state. In both cases, pressing CapsLock is the triggering event.
In [[#Extended states|extended state machines]], a transition can have a [[#Guard conditions|guard]], which means that the transition can "fire" only if the guard evaluates to TRUE. A state can have many transitions in response to the same trigger, as long as they have nonoverlapping guards; however, this situation could create problems in the sequence of evaluation of the guards when the common trigger occurs. The UML specification<ref name=
intentionally does not stipulate any particular order; rather, UML puts the burden on the designer to devise guards in such a way that the order of their evaluation does not matter. Practically, this means that guard expressions should have no side effects, at least none that would alter evaluation of other guards having the same trigger. === Run-to-completion execution model ===
All state machine formalisms, including UML state machines, universally assume that a state machine completes processing of each event before it can start processing the next event. This model of execution is called ''
In the RTC model, the system processes events in discrete, indivisible RTC steps. New incoming events cannot interrupt the processing of the current event and must be stored (typically in an [[Message queue|event queue]]) until the state machine becomes idle again. These semantics completely avoid any internal concurrency issues within a single state machine. The RTC model also gets around the conceptual problem of processing actions associated with transitions, where the state machine is not in a well-defined state (is between two states) for the duration of the action. During event processing, the system is unresponsive (unobservable), so the ill-defined state during that time has no practical significance.
Note, however, that RTC does not mean that a state machine has to monopolize the CPU until the RTC step is complete.<ref name=
The [[Preemption (computing)|preemption]] restriction only applies to the task context of the state machine that is already busy processing events. In a [[Computer multitasking|multitasking environment]], other tasks (not related to the task context of the busy state machine) can be running, possibly preempting the currently executing state machine. As long as other state machines do not share variables or other resources with each other, there are no [[Thread (computer science)#Concurrency and data structures|concurrency hazards]]. The key advantage of RTC processing is simplicity. Its biggest disadvantage is that the responsiveness of a state machine is determined by its longest RTC step. Achieving short RTC steps can often significantly complicate real-time designs.
== UML extensions to the traditional FSM formalism ==
Though the [[finite
[[Image:UML state machine Fig2a.png|thumb|upright=3|center|A pocket calculator (left) and the traditional state machine with multiple transitions Clear and Off (right)]]
UML state machines
=== Hierarchically nested states ===
The most important innovation of UML state machines over the
[[Image:UML state machine Fig2b.png|thumb|upright=3|center|Figure 3: A pocket calculator (left) and the UML state machine with state nesting (right)]]
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States that contain other states are called ''composite states''; conversely, states without internal structure are called ''simple states''. A nested state is called a ''direct substate'' when it is not contained by any other state; otherwise, it is referred to as a ''transitively nested substate''.
Because the internal structure of a composite state can be arbitrarily complex, any hierarchical state machine can be viewed as an internal structure of some (higher-level) composite state. It is conceptually convenient to define one composite state as the ultimate root of state machine hierarchy. In the UML specification,
|chapter=Region
|title=Unified Modeling Language 2.5.1
|series=[[Object Management Group |OMG]] Document Number formal/2017-12-05
|date=December 2017
|publisher=[[Object Management Group]] Standards Development Organization (OMG SDO)
|page=352
|url=https://www.omg.org/spec/UML/2.5.1/PDF
}}
</ref> which contains all the other elements of the entire state machine.
The graphical rendering of this all-enclosing region is optional.
As you can see, the semantics of hierarchical state decomposition are designed to facilitate reusing of behavior. The substates (nested states) need only define the differences from the superstates (
| title = Who Moved My State?
| author = Samek, Miro
| url = http://www.ddj.com/cpp/184401643
| publisher = C/C++ Users Journal, The Embedded Angle column
|date=April 2003}}</ref> the common behavior from its superstate(s) by simply ignoring commonly handled events, which are then automatically handled by higher-level states. In other words, hierarchical state nesting enables '''[[programming by difference]]'''.<ref name="Samek03c">{{Cite web|author=Samek|first=Miro|date=June 2003|title=Dj Vu|url=http://www.ddj.com/cpp/184401665|archive-url=https://web.archive.org/web/20120930224548/http://www.drdobbs.com/dj-vu/184401665|archive-date=2012-09-30|publisher=C/C++ Users Journal, The Embedded Angle column}}</ref>
▲ |date=June 2003}}</ref>
The aspect of state hierarchy emphasized most often is [[abstraction]]—an old and powerful technique for coping with complexity. Instead of
However,
=== Orthogonal regions ===
UML statecharts also introduce the complementary AND-decomposition. Such decomposition means that a composite state can contain two or more orthogonal regions (orthogonal means compatible and independent in this context) and that being in such a composite state entails being in all its orthogonal regions simultaneously.<ref name=Harel98>
{{Cite book
| last1 = Harel
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</ref>
Orthogonal regions address the frequent problem of a combinatorial increase in the number of states when the behavior of a system is fragmented into independent, concurrently active parts. For example, apart from the main keypad, a computer keyboard has an independent numeric keypad. From the previous discussion, recall the two states of the main keypad already identified: "default" and "caps_locked" (see Figure 1). The numeric keypad also can be in two states—"numbers" and "arrows"—depending on whether Num Lock is active. The complete state space of the keyboard in the standard decomposition is therefore the
[[Image:UML state machine Fig4.png|thumb|upright=3|center|Figure 4: Two orthogonal regions (main keypad and numeric keypad) of a computer keyboard]]
Note that if the orthogonal regions are fully independent of each other, their combined complexity is simply additive, which means that the number of independent states needed to model the system is simply the sum ''k + l + m + ...'', where ''k, l, m, ...'' denote numbers of OR-states in each orthogonal region.
In most real-life situations
Even though orthogonal regions imply independence of execution (
{{Cite book
| last1 = Douglass
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| year = 1999
| isbn = 0-201-49837-5
| page = [https://archive.org/details/doinghardtimedev0000doug/page/749 749]
| url = https://archive.org/details/doinghardtimedev0000doug/page/749
</ref> The UML specification only requires that the designer not rely on any particular order in which an event instance will be dispatched to the involved orthogonal regions.▼
}}
▲</ref> The UML specification
=== Entry and exit actions ===
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[[Image:UML state machine Fig5.png|thumb|upright=3|center|Figure 5: Toaster oven state machine with entry and exit actions]]
The value of entry and exit actions is that they provide means for ''guaranteed initialization and cleanup'', very much like class constructors and destructors in
Of course,
Entry and exit actions allow
Because entry actions are executed automatically whenever an associated state is entered, they often determine the conditions of operation or the identity of the state, very much as a class constructor determines the identity of the object being constructed. For example, the identity of the "heating" state is determined by the fact that the heater is turned on. This condition must be established before entering any substate of "heating" because entry actions to a substate of "heating," like "toasting," rely on proper initialization of the "heating" superstate and perform only the differences from this initialization. Consequently, the order of execution of entry actions must always proceed from the outermost state to the innermost state (top-down).
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=== Internal transitions ===
Very commonly, an event causes only some internal actions to execute but does not lead to a change of state (state transition). In this case, all actions executed comprise the '''internal transition'''. For example, when
[[Image:UML state machine Fig6.png|thumb|upright=3|center|Figure 6: UML state diagram of the keyboard state machine with internal transitions]]
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=== Transition execution sequence ===
State nesting combined with entry and exit actions significantly complicates the state transition semantics in HSMs compared to the traditional FSMs. When dealing with [[#Hierarchically nested states|hierarchically nested states]] and [[#Orthogonal regions|orthogonal regions]], the simple term ''current state'' can be quite confusing. In an HSM, more than one state can be active at once. If the state machine is in a leaf state that is contained in a composite state (which is possibly contained in a higher-level composite state, and so on), all the composite states that either directly or transitively contain the leaf state are also active. Furthermore, because some of the composite states in this hierarchy might have orthogonal regions, the current active state is actually represented by a tree of states starting with the single
[[Image:UML state machine Fig7.png|thumb|upright=3|center|Figure 7: State roles in a state transition]]
In UML, a state transition can directly connect any two states. These two states, which may be composite, are designated as the '''main source''' and the '''main target''' of a transition. Figure 7 shows a simple transition example and explains the state roles in that transition. The UML specification prescribes that taking a state transition involves executing the
# Evaluate the guard condition associated with the transition and perform the following steps only if the guard evaluates to TRUE.
# Exit the source state configuration.
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# Enter the target state configuration.
The transition sequence is easy to interpret in the simple case of both the main source and the main target nesting at the same level. For example, transition T1 shown in Figure 7 causes the evaluation of the guard g(); followed by the sequence of actions: <code>a(); b(); t(); c(); d();</code> and <code>e()</code>
However, in the general case of source and target states nested at different levels of the state hierarchy, it might not be immediately obvious how many levels of nesting need to be exited.
The UML specification<ref name= prescribes that a transition involves exiting all nested states from the current active state (which might be a direct or transitive substate of the main source state) up to, but not including, the '''least common ancestor''' (LCA) state of the main source and main target states. As the name indicates, the LCA is the lowest composite state that is simultaneously a superstate (ancestor) of both the source and the target states. As described before, the order of execution of exit actions is always from the most deeply nested state (the current active state) up the hierarchy to the LCA but without exiting the LCA. For instance, the LCA(s1,s2) of states "s1" and "s2" shown in Figure 7 is state "s." Entering the target state configuration commences from the level where the exit actions left off (i.e., from inside the LCA). As described before, entry actions must be executed starting from the highest-level state down the state hierarchy to the main target state. If the main target state is composite, the UML semantics prescribes to "drill" into its submachine recursively using the local initial transitions. The target state configuration is completely entered only after encountering a leaf state that has no initial transitions.
=== Local versus external transitions ===
Before UML 2,<ref name=OMG/>
the only transition semantics in use was the '''external transition''', in which the main source of the transition is always exited and the main target of the transition is always entered.
UML 2 preserved the "external transition" semantics for backward compatibility, but introduced also a new kind of transition called '''local transition''' (see Section 14.2.3.4.4 of ''Unified Modeling Language (UML)''<ref name=OMG/>).
For many transition topologies, external and local transitions are actually identical. However, a local transition doesn't cause exit from and reentry to the main source state if the main target state is a substate of the main source. In addition, a local state transition doesn't cause exit from and reentry to the main target state if the main target is a superstate of the main source state.
[[Image:UML state machine Fig8.png|thumb|upright=3|center|Figure 8: Local (a) versus external transitions (b).]]
Figure 8 contrasts local (a) and external (b) transitions. In the top row, you see the case of the main source containing the main target. The local transition does not cause exit from the source, while the external transition causes exit and
=== Event deferral ===
Sometimes an event arrives at a particularly inconvenient time, when a state machine is in a state that cannot handle the event. In many cases, the nature of the event is such that it can be postponed (within limits) until the system enters another state, in which it is better prepared to handle the original event.
UML state machines provide a special mechanism for '''deferring events''' in states. In every state, you can include a clause <code>[event list]/defer</code>. If an event in the current
== The limitations of UML state machines ==
Harel statecharts, which are the precursors of UML state machines, have been invented as "a visual formalism for complex systems",<ref name=Harel87/> so from their inception, they have been inseparably associated with graphical representation in the form of state diagrams.
However, it is important to understand that the concept of UML state machine transcends any particular notation, graphical or textual. The UML specification<ref name= makes this distinction apparent by clearly separating state machine semantics from the notation. However, the notation of UML statecharts is not purely visual. Any nontrivial state machine requires a large amount of textual information (e.g., the specification of actions and guards). The exact syntax of action and guard expressions
| title = UML Statecharts
| author = Douglass, Bruce Powel
| url =
| publisher = Embedded Systems Programming
|date=January 1999}}</ref> In practice, this means that UML statechart notation depends heavily on the specific [[programming language]].
Nevertheless, most of the statecharts semantics are heavily biased toward graphical notation. For example, state diagrams poorly represent the sequence of processing, be it order of evaluation of [[#Guard conditions|guards]] or order of dispatching events to [[#Orthogonal regions|orthogonal regions]]. The UML specification sidesteps these problems by putting the burden on the designer not to rely on any particular sequencing.
The UML notation and semantics are really geared toward computerized [[UML tools]]. A UML state machine, as represented in a tool, is not just the state diagram, but rather a mixture of graphical and textual representation that precisely captures both the state topology and the actions. The users of the tool can get several complementary views of the same state machine, both visual and textual, whereas the generated code is just one of the many available views.
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== References ==
{{Reflist}}
== External links ==
* {{cite book
|title=Unified Modeling Language 2.5.1
|series=[[Object Management Group |OMG]] Document Number formal/2017-12-05
|date=December 2017
|publisher=[[Object Management Group]] Standards Development Organization (OMG SDO)
|url=https://www.omg.org/spec/UML/2.5.1/PDF
}}
* [http://www.uml-diagrams.org/state-machine-diagrams.html UML 2 State Machine Diagrams]
{{Formal languages and grammars}}
{{UML}}
[[Category:Models of computation]]
▲[[Category:Automata theory]]
[[Category:Digital electronics]]
[[Category:Formal methods]]
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