No instruction set computing: Difference between revisions

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{{Short description|Type of computing architecture}}

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{{More citations needed|date=January 2012}}

{{Technical|date=October 2010}}

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'''No instruction set computing''' ('''NISC''') is a computing architecture and compiler technology for designing highly efficient custom processors and hardware accelerators by allowing a compiler to have low-level control of hardware resources.

== Overview ==

NISC is a statically- scheduled horizontal nanocoded architecture (SSHNA). The term "statically scheduled" means that the [[Scheduling (computing)|operation scheduling]] and hazard[[Hazard (computer architecture)|Hazard]] handling are done by a [[compiler]]. The term "horizontal nanocoded" means that NISC does not have any predefined [[instruction set]] or [[microcode]]. The compiler generates nanocodes which directly control [[functional unitsunit]]s, registers[[Processor register|register]]s and multiplexers[[multiplexer]]s of a given [[datapath]]. Giving low-level control to the compiler enables better utilization of datapath resources, which ultimately result in better performance. The benefits of NISC technology are:

#* Simpler controller: no hardware scheduler, no instruction decoder

#* Better performance: more flexible architecture, better resource utilization

#* Easier to design: no need for designing instruction-sets

Instruction-The instruction set and controller of processors[[Central processing unit|processor]]s are the most tedious and time-consuming parts to design. By eliminating these two, design of custom processing elements become significantly easier.

Furthermore, the datapath of NISC processors can even be generated automatically for a given application. Therefore, designersdesigner's productivity is improved significantly.<br /> Since NISC datapaths are very efficient and can be generated automatically, NISC technology is comparable to [[High-level synthesis|high level synthesis]] (HLS) or [[C to HDL]] synthesis approaches. In fact, one of the benefits of this architecture style is its capability to bridge these two technologies (custom processor design and HLS).

Since NISC datapaths are very efficient and can be generated automatically, NISC technology is comparable to [[High-level synthesis|high level synthesis]] (HLS) or [[C to HDL]] synthesis approaches. In fact, one of the benefits of this architecture style is its capability to bridge these two technologies (custom processor design and HLS).

== History ==

* [[==Zero instruction set computer]] (ZISC)==

In [[computer science]], '''zero instruction set computer''' ('''ZISC''') refers to a [[computer architecture]] based solely on [[pattern matching]] and absence of [[instruction (computer science)|(micro-)instructions]] in the classical{{clarify|reason=What would be an example of a non-classical micro-instruction?|date=December 2016}}<!-- some confusion here could probably be resolved by updating the instruction article --> sense. These chips are known for being thought of as comparable to the [[neural network]]s, being marketed for the number of "synapses" and "neurons".<ref name="BrainChip"/> The [[acronym and initialism|acronym]] ZISC alludes to [[reduced instruction set computer]] (RISC).{{citation needed|date=December 2016}}

ZISC is a hardware implementation of [[Kohonen network]]s (artificial neural networks) allowing massively parallel processing of very simple data (0 or 1). This hardware implementation was invented by Guy Paillet<ref name="Neuron circuit">{{Cite web|url=https://patents.google.com/patent/US5621863|title = Neuron circuit}}</ref> and Pascal Tannhof (IBM),<ref>{{cite web |url=https://www.researchgate.net/profile/Pascal-Tannhof |title=Profile: Pascal Tannhof |website=[[ResearchGate]]}}</ref><ref name="Neuron circuit"/> developed in cooperation with the IBM chip factory of [[Essonnes]], in France, and was commercialized by IBM.

The ZISC architecture alleviates the [[memory bottleneck]]{{clarify|date=December 2016}} by blending pattern memory with pattern learning and recognition logic.{{how|date=December 2016}} Their massively [[parallel computing]] solves the {{Clarify|text="[[Winner-take-all in action selection|winner takes all problem in action selection]]"|post-text=from [[Winner-take-all (computing)|Winner-takes-all]] problem in [[Artificial neural network|Neural Network]]s|reason=Per [https://web.archive.org/web/20170101001452/https://pdfs.semanticscholar.org/1e0c/54bd88223e009997a04dcd2a0f3fa0af3848.pdf source], [[Winner-take-all (computing)|Winner-takes-all]] is defined as a different principle from [[Winner-take-all in action selection]], but both are relevant to [[Artificial neural network|Neural Network]]s|date=December 2016}} by allotting each "neuron" its own memory and allowing simultaneous problem-solving the results of which are settled up disputing with each other.<ref name="Gigaom"/>

===Applications and controversy===

According to [[TechCrunch]], software emulations of these types of chips are currently used for image recognition by many large tech companies, such as [[Facebook]] and [[Google]]. When applied to other miscellaneous pattern detection tasks, such as with text, results are said to be produced in microseconds even with chips released in 2007.<ref name="BrainChip"/>

Junko Yoshida, of the ''[[EE Times]]'', compared the NeuroMem chip with "The Machine", a machine capable of being able to predict crimes from scanning people's faces from the television series ''[[Person of Interest (TV series)|Person of Interest]]'', describing it as "the heart of [[big data]]" and "foreshadow[ing] a real-life escalation in the era of massive data collection".<ref name="NeuroMem"/>

== History ==

In the past, microprocessor design technology evolved from [[complex instruction set computer]] (CISC) to [[reduced instruction set computer]] (RISC). In the early days of the computer industry, compiler technology did not exist and programming was done in [[assembly language]]. To make programming easier, computer architects created complex instructions which were direct representations of high level functions of high level programming languages. Another force that encouraged instruction complexity was the lack of large memory blocks.

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== See also ==

* [[Complex instruction set computer]] (CISC)

* [[Reduced instruction set computer]] (RISC)

* [[Minimal instruction set computer]] (MISC)

* [[One instruction set computer]] (OISC)

* [[Zero instruction set computer]] (ZISC)

* [[C to HDL]]

* [[Content-addressable memory]]

* [[Reduced instruction set computer]] (RISC)

* [[Complex instruction set computer]] (CISC)

* [[Explicitly parallel instruction computing]]

* [[Minimal instruction set computer]] (MISC)

* [[Very long instruction word]]

* [[One -instruction set computer]] (OISC)

* [[TrueNorth]]

==References==

{{Reflist|refs=

<ref name="BrainChip">{{cite web |title=The Ongoing Quest For The 'Brain' Chip |author-first=Philippe |author-last=Lambinet |date=31 January 2015 |publisher=[[TechCrunch]] |url=https://techcrunch.com/2015/01/31/the-ongoing-quest-for-the-brain-chip/}}</ref>

<ref name="Gigaom">{{cite web |title=Make way for more brain-based chips |author-first=Stacey |author-last=Higginbotham |date=14 November 2011 |publisher=[[Gigaom]] |url=https://gigaom.com/2011/11/14/make-way-for-more-brain-based-chips/|archive-url=https://web.archive.org/web/20111116063042/http://gigaom.com/2011/11/14/make-way-for-more-brain-based-chips/|url-status=dead|archive-date=November 16, 2011}}</ref>

<ref name="NeuroMem">{{cite web |title=NeuroMem IC Matches Patterns, Sees All, Knows All |author-first=Junko |author-last=Yoshida |publisher=[[EE Times]] |url=https://www.eetimes.com/document.asp?doc_id=1325690}}</ref>

}}

== Further reading ==

*Chapter 2. {{cite webCite book|urlisbn=http://www.amazon.com/Designing978-Embedded-Processors-Power-Perspective/dp/14020586831402058684 |title=Designing Embedded Processors: A Low Power Perspective: By: JeorgJörg Henkel, Sri Parameswaran |accessdatelast1=2007-06-22Henkel |formatfirst1=Jörg |worklast2=Parameswaran |first2=Sri |date=11 July 2007 |publisher=Springer }}

== External links ==

* [https://patents.google.com/patent/US5621863 US Patent for ZISC hardware], issued to IBM/G.Paillet on April 15, 1997

* [http://www.cecs.uci.edu/~nisc NISC Toolset (a C-to-Verilog and custom processor design tool) in CECS UC, Irvine]

* [https://doi.org/10.1023%2FA%3A1021990410058 Image Processing Using RBF like Neural Networks: A ZISC-036 Based Fully Parallel Implementation Solving Real World and Real Complexity Industrial Problems] by K. Madani, G. de Trémiolles, and P. Tannhof

* [http://www.lsmarketing.com/LSMFiles/9809-ai1.htm From CISC to RISC to ZISC] by S. Liebman on lsmarketing.com

* [https://web.archive.org/web/20060527023259/http://www.aboutai.net/DesktopDefault.aspx?article=aa071800a.htm&tabid=2 Neural Networks on Silicon] at aboutAI.net

* [https://patentscope.wipo.int/search/zh/detail.jsf;jsessionid=2EEDB543070890EAD531331F04F3C2DB.wapp2nB?docId=FR290835374&_cid=P21-K8UX94-10474-3 French Patent Request] NISC for purely applicative engine - the sole operation of application (no lambda-calculus that is a particular case of quasi-applicative systems with two operations : application and abstraction - Curry 1958 p.&nbsp;31)

{{CPU technologies}}

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[[Category:Electronic design]]

[[Category:Central processing unit]]

[[Category:Instruction processing]]

[[es:NISC]]