NAND gate: Difference between revisions

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{{Short description|Logical gate whose output is false if all its inputs are true}}

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{{One source|date=July 2023}}

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|colspan=2|'''INPUT''' || '''OUTPUT'''

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! colspan="3" | NAND gate [[truth table]]

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|colspan=2|'''Input''' || '''Output'''

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| A || B || A NAND B

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[[File:7400.jpg|thumb|The TTL 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground]]

In [[digital electronics]], a '''NAND gate''' ('''NegatedNOT AND''' or) '''NOT ANDgate''') is a [[logic gate]] which produces an output thatwhich is false only if all its inputs are true; thus its output is [[Complement (set theory)|complement]] to that of thean [[AND gate]]. A LOW (0) output results only if bothall the inputs to the gate are HIGH (1); if oneany orinput both inputs areis LOW (0), a HIGH (1) output results. ItA NAND gate is made using transistors and junction diodes. By [[De Morgan's laws]], a two-input NAND gate's logic may be expressed as <math>\overline{A} \lor \overline{B} = \overline{A \cdot B}</math>, making a NAND gate equivalent to [[Inverter (logic gate)|inverters]] followed by an [[OR gate]].

The NAND gate is significant because any boolean[[Boolean function]] can be implemented by using a combination of NAND gates. This property is called "[[functional completeness]]". It shares this property with the [[NOR gate]]. Digital systems employing certain logic circuits take advantage of NAND's functional completeness.

NAND gates with two or more inputs are available as [[integrated circuit]]s in [[transistor–transistor logic]], [[CMOS]], and other [[logic family|logic families]].

Digital systems employing certain logic circuits take advantage of NAND's functional completeness.

The function {{nowrap|NAND(''a''₁, ''a''₂, ..., ''a_n'')}} is [[Logical equivalence|logically equivalent]] to {{nowrap|NOT(''a''₁ AND ''a''₂ AND ... AND ''a_n'').}}

== Symbols ==

There are three symbols for NAND gates: the ''MIL/[[ANSI]]'' symbol, the ''[[International Electrotechnical Commission|IEC]]'' symbol and the deprecated ''[[DIN]]'' symbol sometimes found on old schematics. ForThe moreANSI informationsymbol seefor [[logicthe NAND gate#Symbols|logic is a standard AND gate symbols]]with an inversion bubble connected.

{| align=center style="margin:auto; text-align:center;" class="skin-invert-image"

|[[File:NAND ANSI Labelled.svg]]

|[[File:NAND IEC.svg]]

|[[file:NAND DIN.svg]]

|-

|''MIL/ANSI Symbol''&nbsp;&nbsp;&nbsp;

|[[Image:NAND ANSI Labelled.svg]]

|''IEC Symbol''&nbsp;&nbsp;&nbsp;

|[[Image:NAND IEC.svg]]

|[[Image:NAND DIN.svg]]

|-

|''MIL/ANSI Symbol''

|''IEC Symbol''

|''DIN Symbol''

|}

{{clear}}

== Logic ==

== Hardware description and pinout ==

NAND gates are basic logic gates, and as such they are recognised in [[Transistor–transistor logic|TTL]] and [[CMOS]] [[integrated circuit|IC]]s.

The function {{nowrap|NAND(''a''₁, ''a''₂, ..., ''a_n'')}} is [[Logical equivalence|logically equivalent]] to {{nowrap|NOT(''a''₁ AND ''a''₂ AND ... AND ''a_n'').}}

[[Image:4011 Pinout.svg|frame|right|This schematic diagram shows the arrangement of NAND gates within a standard 4011 CMOS integrated circuit.]]

One way of expressing A NAND B is <math>\overline{A \land B}</math>, where the symbol <math>{\land}</math> signifies AND and the bar signifies the negation of the expression under it: in essence, simply <math>{\displaystyle \lnot (A \land B)}</math>.

=== CMOS version ===

The standard, [[4000 series]], [[CMOS]] [[integrated circuit|IC]] is the 4011, which includes four independent, two-input, NAND gates.

==== AvailabilityImplementations ====

The basic implementations can be understood from the image on the left below: If either of the switches S1 or S2 is open, the [[pull-up resistor]] R will set the output signal Q to 1 (high). If S1 and S2 are both closed, the pull-up resistor will be overridden by the switches, and the output will be 0 (low).

These devices are available from most semiconductor manufacturers such as [[Fairchild Semiconductor]], [[Philips]] or [[Texas Instruments]]. These are usually available in both through-hole [[Dual in-line package|DIL]] and [[small-outline integrated circuit|SOIC]] format. Datasheets are readily available in most [[datasheet#Datasheet Search Engines|datasheet databases]].

In the [[depletion-load NMOS logic]] realization in the middle below, the switches are the transistors T2 and T3, and the transistor T1 fulfills the function of the pull-up resistor.

The standard 2-, 3-, 4- and 8-input NAND gates are available:

In the [[CMOS]] realization on the right below, the switches are the [[Extrinsic_semiconductor#N-type_semiconductors|n-type]] transistors T3 and T4, and the pull-up resistor is made up of the [[Extrinsic_semiconductor#Ptype_semiconductors|p-type]] transistors T1 and T2, which form the complement of transistors T3 and T4.

* [[CMOS]]

** 4011: Quad 2-input NAND gate

** 4023: Triple 3-input NAND gate

** 4012: Dual 4-input NAND gate

** 4068: Mono 8-input NAND gate

* [[Transistor-transistor logic|TTL]]

** 7400: Quad 2-input NAND gate

** 7410: Triple 3-input NAND gate

** 7420: Dual 4-input NAND gate

** 7430: Mono 8-input NAND gate

<gallery class="center skin-invert-image" caption="Realization of NAND gates in different logic families" perrow="3">

== Implementations ==

Funktionsprinzip eines NAND-Gatters.svg|Implementation using switches and a pull-up resistor

The NAND gate has the property of [[functional completeness]]. That is, any other logic function (AND, OR, etc.) can be [[NAND logic|implemented]] using only NAND gates.<ref name="Mano">

Nmos enhancement saturated nand.svg|[[Depletion-load NMOS logic|NMOS]]

Mano, M. Morris and Charles R. Kime. ''Logic and Computer Design Fundamentals, Third Edition.'' Prentice Hall, 2004. p. 73.</ref> An entire processor can be created using NAND gates alone. In TTL ICs using multiple-emitter [[transistors]], it also requires fewer transistors than a NOR gate.

Cmos nand.svg|[[CMOS]]

</gallery>

In CMOS, NAND gates are more efficient than [[NOR gate|NOR gates]]. This is due to the faster charge mobility in n-MOSFETs compared to p-MOSFETs, so that the parallel connection of two p-MOSFETs (T1 and T2) realised in the NAND gate is more favourable than their series connection in the NOR gate. For this reason, NAND gates are generally preferred over NOR gates in CMOS circuits.<ref>{{Cite web |title=Digital circuits, sizing, output impedance, rise and fall time. |url=https://inst.eecs.berkeley.edu/~ee105/sp04/handouts/lectures/Lecture18.pdf |last=Smith |first=J.S. |archive-url=https://web.archive.org/web/20070706145946/https://inst.eecs.berkeley.edu/~ee105/sp04/handouts/lectures/Lecture18.pdf |archive-date=2007-07-06 }}</ref>

{|

|-

| [[Image:NMOS NAND.svg|thumbnail|100px|[[NMOS logic|NMOS]] NAND gate]]

| [[Image:CMOS NAND.svg|right|thumbnail|100px|[[CMOS]] NAND gate]]

| [[Image:TTL npn nand.svg|thumb|200px|[[Transistor–transistor logic|TTL]] NAND gate]]

| [[Image:CMOS NAND Layout.svg|right|thumbnail|100px|The [[physical layout]] of a CMOS NAND]]

| [[Image:NXP-74AHC00D-HD.jpg|thumb|[[Die (integrated circuit)|Die]] of a 74AHC00D quad 2-input NAND gate manufactured by [[NXP Semiconductors]].]]

|}

== Hardware design and pinout ==

=== Alternatives ===

[[Image:4011 Pinout.svg|thumb|Diagram of the NAND gates in a CMOS type 4011 integrated circuit]]

If no specific NAND gates are available, one can be made from [[NOR Gate|NOR]] gates, because NAND and NOR gates are considered the "universal gates", meaning that they can be used to make all the others.<ref name="Mano"/>

NAND gates are basic logic gates, and as such they are recognised in [[Transistor–transistor logic|TTL]] and [[CMOS]] [[integrated circuit|IC]]s.

{| align=center style="text-align:center"

!width="150" |NOR construction

The standard, [[4000 series]], [[CMOS]] [[integrated circuit|IC]] is the 4011, which includes four independent, two-input, NAND gates. These devices are available from many semiconductor manufacturers. These are usually available in both through-hole [[Dual in-line package|DIL]] and [[small Outline Integrated Circuit|SOIC]] formats. Datasheets are readily available in most [[datasheet#Datasheet Search Engines|datasheet databases]].

|-

|[[File:NAND from NOR.svg]]

The standard two-, three-, four- and eight-input NAND gates are available:

|}

* [[CMOS]]

** 4011: Quad two-input NAND gate

** 4023: Triple three-input NAND gate

** 4012: Dual four-input NAND gate

** 4068: Mono eight-input NAND gate

* [[Transistor–transistor logic|TTL]]

** 7400: Quad two-input NAND gate

** 7410: Triple three-input NAND gate

** 7420: Dual four-input NAND gate

** 7430: Mono eight-input NAND gate

== Functional completeness ==

[[File:NAND from NOR.svg|thumb|class=skin-invert-image|Construction of a NAND gate from NOR gates]]

{{main|NAND logic|NOR logic}}

The NAND gate has the property of [[functional completeness]], which it shares with the [[NOR Gate|NOR gate]]. That is, any other logic function (AND, OR, etc.) can be implemented using only NAND gates.<ref name="Mano">Mano, M. Morris and Charles R. Kime. ''Logic and Computer Design Fundamentals, Third Edition.'' Prentice Hall, 2004. p. 73.</ref> An entire processor can be created using NAND gates alone. In TTL ICs using multiple-emitter [[transistors]], it also requires fewer transistors than a NOR gate.

As NOR gates are also functionally complete, if no specific NAND gates are available, one can be made from [[NOR Gate|NOR]] gates using [[NOR logic]].<ref name="Mano" />

== See also ==

* [[ANDBoolean gatealgebra]]

* [[ORFlash gatememory]]

* [[NOTlogic gate#Symbols|Logic gate symbols]]

* [[NORSheffer gatestroke]]

*[[XOR gate]]

*[[XNOR gate]]

*[[Boolean algebra (logic)]]

*[[Logic gates]]

*[[NAND logic]]

*[[Digital electronics]]

== References ==

{{refs}}

== External links ==

{{Reflist}}

{{commonscat|NAND gates}}

* [http://www.allaboutcircuits.com/vol_4/chpt_3/5.html TTL NAND and AND gates] at All About Circuits

==External links==

{{commons category|NAND gates}}

{{Logical connectives}}

[[Category:Logic gates|NAND gate]]

[[Category:Logic gates|NAND gate]]

[[es:Puerta lógica#Puerta NO-Y (NAND)]]