Application-specific instruction set processor: Difference between revisions

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{{Short description|Processor with an instruction set customized (optimized) for a specific task}}

{{Inline citations|date=January 2015}}

{{Use American English|date=March 2019}}

An '''application-specific instruction-set processor''' ('''ASIP''') is a component used in [[system-on-a-chip]] design. The [[instruction set]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[Central processing unit|CPU]] and the performance of an [[Application-specific integrated circuit|ASIC]].

{{Use mdy dates|date = March 2019}}

{{InlineMore citationsfootnotes|date=January 2015}}

An '''application-specific instruction- set processor''' ('''ASIP''') is a component used in [[system- on- a- chip]] design. The [[instruction set architecture]] of an ASIP is tailored to benefit a specific application. This specialization of the core provides a tradeoff between the flexibility of a general purpose [[Centralcentral processing unit|CPU]] (CPU) and the performance of an [[Applicationapplication-specific integrated circuit|ASIC]] (ASIC).

Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: ''static'' logic which defines a minimum ISA (instruction-set architecture) and ''configurable'' logic which can be used to design new instructions. The configurable logic can be programmed either in the field in a similar fashion to ana [[FPGAfield-programmable gate array]] (FPGA) or during the chip synthesis. ASIPs have two ways of generating code: either through a retargetable code generator or through a retargetable compiler generator. The retargetable code generator uses the application, ISA, and Architecture Template to create the code generator for the object code. The retargetable compiler generator uses only the ISA and Architecture Template as the basis for creating the compiler. The application code will then be used by the compiler to create the object code.<ref>{{Cite book|last1=Jain|first1=M.K.|last2=Balakrishnan|first2=M.|last3=Kumar|first3=A.|title=VLSI Design 2001. Fourteenth International Conference on VLSI Design |chapter=ASIP design methodologies: Survey and issues |date=2001|___location=Bangalore, India|publisher=IEEE Comput. Soc|pages=76–81|doi=10.1109/ICVD.2001.902643|isbn=978-0-7695-0831-3|s2cid=14053636 }}</ref>

ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo Decodingdecoding", in Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. </ref> or video coding.<ref> Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 </ref> The traditionalTraditional hardware accelerators for the baseband orthese multimediaapplications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machinesmachine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from the scratch can be very complicated. ThereOne areapproach someis commercialto toolsdescribe tothe designprocessor ASIPs,using fora example,high Processorlevel Designerlanguage fromand Synopsys.<ref>then Synopsys'to processorautomatically designergenerate webpage,the http://wwwASIP's software toolset.synopsys.com/IP/ProcessorIP/asip/Pages/default.aspx. </ref>Masarík, ThereUML isin andesign openof source tool as wellASIP, TTA-basedIFAC codesignProceedings environmentVolumes 39(TCE17).<ref> TTA:209-based codesign environment214, http://tce.cs.tut.fi/September 2006</ref>

== Examples ==

[[RISC-V|RISC-V Instruction Set Architecture]] (ISA) provides minimum base instruction sets that can be extended with additional application-specific instructions.<ref>{{Cite book |last=Krste |first=CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Waterman, Andrew Lee, Yunsup Patterson, David A Asanovi |title=The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0 |date=2014-05-06 |oclc=913589579}}</ref> The base instruction sets provide simplified control flow, memory and arithmetic operations on registers. Its modular design allows the base instructions to be extended for standard application-specific operations such as integer multiplication/division (M), single-precision floating point (F), or bit manipulation (B). For the non-standard instruction extensions, encoding space of the ISA is divided into three parts: ''standard, reserverd,'' and ''custom.'' The ''custom'' encoding space is used for vendor-specific extensions.

==See also==

* [[Application-specific integrated circuit]]

* [[System on Chip]]

* [[Digital signal processor]]

==References==

{{reflist}}

== Literature ==

* {{cite book |title=Embedded DSP Processor Design Application Specific Instruction-set Processors |author=Dake Liu |year=2008 |publisher=Elsevier Mogan Kaufmann |___location=MA |isbn=978-0-12-374123-3 }}

* {{cite book |title=OptimizedEmbedded ASIPDSP SynthesisProcessor fromDesign: ArchitectureApplication DescriptionSpecific LanguageInstruction ModelsSet Processors |author=OliverDake Schliebusch, Heinrich Meyr, Rainer LeupersLiu |year=20072008 |publisher=SpringerElsevier Mogan Kaufmann |___location=DordrechtMA |isbn=978-10-402012-5685374123-73 }}

* {{cite book |title=CustomizableOptimized EmbeddedASIP ProcessorsSynthesis from Architecture Description Language Models |authorauthor1=PaoloOliver Ienne,Schliebusch |author2=Heinrich Meyr |author3=Rainer Leupers (eds.) |year=20062007 |publisher=Morgan KaufmannSpringer |___location=San Mateo, CADordrecht |isbn=978-01-124020-3695265685-07 }}

* {{cite book |title=BuildingCustomizable ASIPs:Embedded TheProcessors Mescal|year=2006 Methodology|publisher=Morgan Kaufmann |author___location=MatthiasSan GriesMateo, Kurt Keutzer (eds.)CA |yeareditor-last2=2005Ienne |publishereditor-first2=Springer |___location=New YorkPaolo |isbn=978-0-38712-26057369526-0 |editor-last=Leupers |editor-first=Rainer}}

* {{cite book |title=Building ASIPs: The Mescal Methodology |author= |year=2005 |publisher=Springer |___location=New York |editor-last2=Keutzer |editor-first2=Kurt |isbn=978-0-387-26057-0 |editor-last=Gries |editor-first=Matthias}}

==External links==

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{{CPU technologies}}

[[Category:InstructionApplication-specific processingintegrated circuits]]

[[Category:Coprocessors]]

[[Category:Gate arrays]]

[[Category:Instruction processing]]

[[Category:Integrated circuits]]

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