Numerically controlled oscillator: Difference between revisions

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{{short description|Digital signal generator}}

A '''numerically controlled oscillator''' ('''NCO''') is a digital [[signal generator]] which creates a [[Synchronous circuit|synchronous]] (i.e. clocked), discrete-time, discrete-valued representation of a [[waveform]], usually [[sinusoidal]].<ref name="IEEE">{{cite book |last=Radatz |first=J. |title=The IEEE Standard Dictionary of Electrical and Electronics Terms |publisher=IEEE Standards Office |___location=New York, NY |year=1997 |isbn=}}</ref> NCOs are often used in conjunction with a [[digital-to-analog converter]] (DAC) at the output to create a [[direct digital synthesizer]] (DDS).{{#tag:ref|While some authors use the terms DDS and NCO interchangeably,<ref name="latticeSC" /> by convention an NCO refers to the digital (i.e. the discrete-time, discrete amplitude) portion of a DDS<ref name="IEEE"/>}}

A '''numerically controlled oscillator''' ('''NCO''') is a digital [[signal generator]] which creates a [[Synchronous circuit|synchronous]] (i.e., clocked), discrete-time, discrete-valued representation of a [[waveform]], usually [[sinusoidal]].<ref name="IEEE">{{cite book |last=Radatz |first=J. |title=The IEEE Standard Dictionary of Electrical and Electronics Terms |publisher=IEEE Standards Office |___location=New York, NY |year=1997 |isbn=}}</ref> NCOs are often used in conjunction with a [[digital-to-analog converter]] (DAC) at the output to create a [[direct digital synthesizer]] (DDS).{{#tag:ref|While some authors use the terms DDS and NCO interchangeably,<ref name="latticeSC" /> by convention an NCO refers to the digital (i.e. the discrete-time, discrete amplitude) portion of a DDS<ref name="IEEE"/>}}

Numerically controlled oscillators offer several advantages over other types of oscillators in terms of agility, accuracy, stability and reliability.<ref name="latticeSC">{{ cite web | title = Numerically Controlled Oscillator | url = http://www.latticesemi.com/products/intellectualproperty/ipcores/numericallycontrolledosci/index.cfm | publisher = Lattice Semiconductor Corporation | year = 2009 }}</ref> NCOs are used in many communications systems including digital up/down converters used in 3G wireless and software radio systems, digital PLLs, radar systems, drivers for optical or acoustic transmissions, and multilevel [[Frequency-shift keying|FSK]]/[[Phase-shift keying|PSK]] modulators/demodulators.<ref name="latticeSC"/>

Numerically controlled oscillators offer several advantages over other types of oscillators in terms of agility, accuracy, stability and reliability.<ref name="latticeSC">{{ cite web | title = Numerically Controlled Oscillator | url = http://www.latticesemi.com/productsProducts/intellectualpropertyDesignSoftwareAndIP/ipcoresIntellectualProperty/numericallycontrolledosciIPCore/indexIPCores02/NumericallyControlledOscillator.cfmaspx | publisher = Lattice Semiconductor Corporation | year = 2009 }}</ref> NCOs are used in many communications systems including digital up/down converters used in 3G wireless and software radio systems, digital PLLs[[phase-locked loop]]s, radar systems, drivers for optical or acoustic transmissions, and multilevel [[Frequency-shift keying|FSK]]/[[Phase-shift keying|PSK]] modulators/demodulators.<ref name="latticeSC"/>

==Operation==

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==Phase accumulator==

<!-- linked from redirect [[Phase accumulator]] -->

A binary phase accumulator consists of an N-bit binary [[adder (electronics)|adder]] and a [[hardware register|register]] configured as shown in Figure 1.<ref name="Grzeg"/> Each clock cycle produces a new N-bit output consisting of the previous output obtained from the register summed with the frequency control word (FCW) which is constant for a given output frequency. The resulting output waveform is a staircase with step size <math>\Delta F</math>, the integer value of the FCW.<ref name="ADI"/> In some configurations, the phase output is taken from the output of the register which introduces a one clock cycle [[latency (engineering)|latency]] but allows the adder to operate at a higher clock rate.<ref name="latticeSC" />

[[Image:Phase Accum Graph.png|frame|Figure 2: Normalized phase accumulator output]]

The adder is designed to overflow when the sum of the [[absolute value]] of its operands exceeds its capacity (2^N−1). The overflow bit is discarded so the output word width is always equal to its input word width. The remainder <math>\phi _n</math>, called the residual, is stored in the register and the cycle repeats, starting this time from <math>\phi _n</math> (see figure 2).<ref name="Grzeg"/> Since a phase accumulator is a [[finite -state machine]], eventually the residual at some sample K must return to the initial value <math>\phi _0</math>. The interval K is referred to as the grand repetition rate (GRR) given by

:<math>\mbox{GRR}=\frac{2^N}{\mbox{GCD}(\Delta F,2^N)}</math>

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==Phase-to-amplitude converter==

The phase-amplitude converter creates the sample-___domain waveform from the truncated phase output word received from the PA. The PAC can be a simple [[read only memory]] containing 2^M contiguous samples of the desired output waveform which typically is a sinusoid. Often though, various tricks are employed to reduce the amount of memory required. This include various trigonometric expansions,<ref>{{ Citationcite patent | inventor-last = Miller | inventor-first = B. M. | issue-date = October 14, 2008 | title = Numerically controlled oscillator and method of operation | country-code = US | patent-number = 7437391 }}</ref> trigonometric approximations<ref name="Grzeg">{{ cite web | first1 = G. | last1 = Popek | first2 = M. | last2 = Kampik | title = Low-Spur Numerically Controlled Oscillator Using Taylor Series Approximation | url = http://mechatronika.polsl.pl/owd/pdf2009/030.pdf | date = October 2009 | work = XI International PhD Workshop OWD 2009 | publisher = Silesian University of Technology | ___location = Gliwice, Poland | access-date = 2010-02-12 | archive-date = 2011-08-20 | archive-url = https://web.archive.org/web/20110820213740/http://mechatronika.polsl.pl/owd/pdf2009/030.pdf | url-status = dead }}</ref> and methods which take advantage of the quadrature symmetry exhibited by sinusoids.<ref>{{ Citationcite patent | inventor1-last = McCallister | inventor1-first = R. D. | inventor2-last = Shearer | inventor2-first = D. | publication-date = 12/04/1984 | title = Numerically controlled oscillator using quadrant replication and function decomposition | country-code = US | patent-number = 4486846 }}</ref> Alternatively, the PAC may consist of [[random access memory]] which can be filled as desired to create an [[arbitrary waveform generator]].

==Spurious products==

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where W is the number of bits truncated.

In calculating the [[Spuriousspurious-free dynamic range]], we are interested in the spurious product with the largest amplitude relative to the carrier output level given by:

:<math>\zeta _{max}=2^{-M} \frac{\pi \mbox{GCD}(\Delta F,2^W)}{\sin \left( \pi \cdot 2^{-P}\mbox{GCD}(\Delta F,2^W) \right)}</math>

where P is wordthe widthsize of the DACphase-to-amplitude converter's lookup table in bits, i.e., M in Figure 1. For W >4,

:<math>\zeta _{max} \approx -6.02 \cdot P\;\mbox{dBc}.</math>

Another related spurious generation method is the slight modulation due to the GRR outlined above. The amplitude of these spurs is low for large N and their frequency is generally too low to be detectable but they may cause issues for some applications.<ref name="Grzeg"/>

One way to reduce the truncation in the address lookup is to have several smaller lookup tables in parallel and use the upper bits to index into the tables and the lower bits to weigh them for linear or quadratic interpolation. Ie use a 24-bit phase accumulator to look up into two 16-bit LUTS. Address into the truncated 16 MSBs, and that plus 1. Linearly interpolate using the 8 LSBs as weights. (One could instead use 3 LUTs instead and quadratically interpolate). This can result in decreased distortion for the same amount of memory at the cost of some multipliers.

===Amplitude truncation spurs===

Another source of spurious products is the amplitude [[Quantization (signal processing)|quantization]] of the sampled waveform contained in the PAC look up table(s). If the number of DAC bits is P, the

AM spur level is approximately equal to −6.02 &nbsp;P − 1.76 &nbsp;[[dBc]].<ref name="intersil">{{ cite web | title = The NCO as a Stable, Accurate Synthesizer | url = http://www.intersil.com/content/dam/Intersil/documents/tb31/tb318.pdf | id = TB318.1 | publisher = Intersil Corporation | year = 1998 }}</ref>

===Mitigation techniques===

Phase truncation spurs can be reduced substantially by the introduction of [[White noise|white gaussian noise]] prior to truncation. The so-called [[dither]] noise is summed into the lower W+1 bits of the PA output word to linearize the truncation operation. Often the improvement can be achieved without penalty because the DAC noise floor tends to dominate system performance. Amplitude truncation spurs can not be mitigated in this fashion. Introduction of noise into the static values held in the PAC ROMs would not eliminate the cyclicality of the trunctiontruncation error terms and thus would not achieve the desired effect.<ref name="kroupa"/>

==See also==

* [[Direct digital synthesizersynthesis]] (DDS)

* [[Digital-to-analog converter]] (DAC)

* [[Digitally controlled oscillator]] (DCO)

*[[Digital-to-analog converter]]

==References==

{{reflist|2}}

{{good article}}

{{DEFAULTSORT:Numerically Controlledcontrolled Oscillatoroscillator}}

[[Category:Digital signal processing]]

[[Category:Synthesizers]]

[[Category:OscillatorsElectronic oscillators]]

[[Category:Digital electronics]]