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{{short description|Array of logic gates that are reprogrammable}}
{{Redirect-distinguish|FPGA|Flip-chip pin grid array}}
{{Use American English|date=April 2019}}
[[File:Altera StratixIVGX FPGA.jpg|thumb|A [[Stratix (FPGA)|Stratix IV]] FPGA from [[Altera]]]]
{{multiple image
| header = Spartan FPGA from [[Xilinx]]
| image1 = Xerox ColorQube 8570 - Main controller - Xilinx Spartan XC3S400A-0205.jpg
| caption1 = [[Integrated circuit packaging|Package]]
| image2 = Xilinx Spartan FPGA die shot.jpg
| caption2 = [[Die (integrated circuit)|Die]]
}}
A '''field-programmable gate array''' ('''FPGA''') is a type of configurable [[integrated circuit]] that can be repeatedly programmed after manufacturing. FPGAs are a subset of logic devices referred to as [[programmable logic devices]] (PLDs). They consist of a grid-connected array of [[programmable logic device|programmable]] [[logic block|logic blocks]] that can be configured "in the field" to interconnect with other logic blocks to perform various digital functions. FPGAs are often used in limited (low) quantity production of custom-made products, and in research and development, where the higher cost of individual FPGAs is not as important and where creating and manufacturing a custom circuit would not be feasible. Other applications for FPGAs include the telecommunications, automotive, aerospace, and industrial sectors, which benefit from their flexibility, high signal processing speed, and parallel processing abilities.
A FPGA configuration is generally written using a [[hardware description language]] (HDL) e.g. [[VHDL]], similar to the ones used for [[application-specific integrated circuit]]s (ASICs). [[Circuit diagram|Circuit diagrams]] were formerly used to write the configuration.
The logic blocks of an FPGA can be configured to perform complex [[combinational logic|combinational functions]], or act as simple [[logic gate]]s like [[AND gate|AND]] and [[XOR gate|XOR]]. In most FPGAs, logic blocks also include [[Memory cell (computing)|memory elements]], which may be simple [[flip-flop (electronics)|flip-flops]] or more sophisticated blocks of memory.<ref name="FPGA" /> Many FPGAs can be reprogrammed to implement different [[Boolean function|logic functions]], allowing flexible [[reconfigurable computing]] as performed in [[computer software]].
FPGAs also have a role in [[embedded system]] development due to their capability to start system software development simultaneously with hardware, enable system performance simulations at a very early phase of the development, and allow various system trials and design iterations before finalizing the system architecture.<ref>{{cite book |last1=Simpson |first1=P. A. |date=2015 |title=FPGA Design, Best Practices for Team Based Reuse, 2nd edition |___location=Switzerland |publisher=Springer International Publishing AG |page=16 |isbn=978-3-319-17924-7 }}</ref>
FPGAs are also commonly used during the development of ASICs to speed up the simulation process.
== History ==
The FPGA industry sprouted from [[programmable read-only memory]] (PROM) and [[programmable logic device]]s (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable).<ref name="history">{{cite web |url=http://filebox.vt.edu/users/tmagin/history.htm |title=History of FPGAs |access-date=2013-07-11 |url-status=dead |archive-url=https://web.archive.org/web/20070412183416/http://filebox.vt.edu/users/tmagin/history.htm |archive-date=April 12, 2007}}</ref>
[[Altera]] was founded in 1983 and delivered the industry's first reprogrammable logic device in 1984 – the EP300 – which featured a quartz window in the package that allowed users to shine an ultra-violet lamp on the [[Die (integrated circuit)|die]] to erase the [[EPROM]] cells that held the device configuration.<ref>{{cite web|url=https://www.altera.com/solutions/technology/system-design/articles/_2013/in-the-beginning.html|archive-url=https://web.archive.org/web/20150421045728/https://www.altera.com/solutions/technology/system-design/articles/_2013/in-the-beginning.html |archive-date=2015-04-21|title=In the Beginning|date=21 April 2015|work=altera.com|author=Ron Wilson}}</ref>
[[Xilinx]] produced the first commercially viable field-programmable [[gate array]] in 1985<ref name="history" />{{snd}}the XC2064.<ref name=":0">{{Cite web|url=http://www.xilinx.com/publications/archives/xcell/Xcell32.pdf |archive-url=https://web.archive.org/web/20110107140043/http://www.xilinx.com/publications/archives/xcell/Xcell32.pdf |archive-date=2011-01-07 |url-status=live|title=XCELL issue 32|publisher=Xilinx}}</ref> The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market.<ref name="four">Funding Universe. "[http://www.fundinguniverse.com/company-histories/Xilinx-Inc-Company-History.html Xilinx, Inc.]" Retrieved January 15, 2009.</ref> The XC2064 had 64 configurable logic blocks (CLBs), with two three-input [[lookup table]]s (LUTs).<ref name="clive">Clive Maxfield, Programmable Logic DesignLine, "[http://www.pldesignline.com/products/187203173 Xilinx unveil revolutionary 65nm FPGA architecture: the Virtex-5 family] {{Webarchive|url=https://web.archive.org/web/20091225212024/http://www.pldesignline.com/products/187203173 |date=2009-12-25 }}. May 15, 2006. Retrieved February 5, 2009.</ref>
In 1987, the [[Naval Surface Warfare Center]] funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.<ref name="history" />
Altera and Xilinx continued unchallenged and quickly grew from 1985 to the mid-1990s
The 1990s were
By 2013, Altera (31 percent), Xilinx (36 percent) and Actel (10 percent) together represented approximately 77 percent of the FPGA market.<ref>{{cite web|url=http://sourcetech411.com/2013/04/top-fpga-companies-for-2013/|title=Top FPGA Companies For 2013|work=sourcetech411.com|date=2013-04-28|access-date=2015-07-08|archive-date=2015-07-09|archive-url=https://web.archive.org/web/20150709173535/http://sourcetech411.com/2013/04/top-fpga-companies-for-2013/|url-status=dead}}</ref>
Companies like Microsoft have started to use FPGAs to accelerate high-performance, computationally intensive systems (like the [[data center]]s that operate their [[Bing search engine]]), due to the [[performance per watt]] advantage FPGAs deliver.<ref>{{cite magazine|url=https://www.wired.com/2014/06/microsoft-fpga/|title=Microsoft Supercharges Bing Search With Programmable Chips|date=16 June 2014|magazine=WIRED}}</ref> Microsoft began using FPGAs to [[Hardware acceleration|accelerate]] Bing in 2014, and in 2018 began deploying FPGAs across other data center workloads for their [[Microsoft Azure|Azure]] [[cloud computing]] platform.<ref name="ProjCatapult" />
Since 2019, modern generation of FPGAs have been integrated with other architectures like [[AI engine|AI engines]] to target workloads in artificial intelligence ___domain.<ref>{{Cite book |last1=Gaide |first1=Brian |last2=Gaitonde |first2=Dinesh |last3=Ravishankar |first3=Chirag |last4=Bauer |first4=Trevor |chapter=Xilinx Adaptive Compute Acceleration Platform: Versal <sup>TM</sup> Architecture |date=2019-02-20 |title=Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays |chapter-url=https://dl.acm.org/doi/10.1145/3289602.3293906 |language=en |publisher=ACM |pages=84–93 |doi=10.1145/3289602.3293906 |isbn=978-1-4503-6137-8|chapter-url-access=subscription }}</ref>
===Growth===
The following timelines indicate progress in different aspects of FPGA design.
===
* 1987: 9,000 gates, Xilinx<ref name="four" />
* 1992: 600,000, Naval Surface Warfare Department<ref name="history" />
* Early 2000s:
* 2013: 50 million, Xilinx<ref name="gates2013">{{cite web|last1=Maxfield|first1=Max|title=Xilinx UltraScale FPGA Offers 50 Million Equivalent ASIC Gates|url=https://www.eetimes.com/document.asp?doc_id=1320345|website=www.eetimes.com|publisher=EE Times}}</ref>
===
* 1985: First commercial FPGA : Xilinx XC2064<ref name=":0" /><ref name="four" />
* 1987: $14 million<ref name="four" />
*
* 2005: $1.9 billion<ref name="instat">Dylan McGrath, ''EE Times'', "[http://www.eetimes.com/news/design/business/showArticle.jhtml?articleID=188102617 FPGA Market to Pass $2.7 Billion by '10, In-Stat Says]". May 24, 2006. Retrieved February 5, 2009.</ref>
* 2010 estimates: $2.75 billion<ref name="instat" />
* 2013: $5.4 billion
* 2020 estimate: $9.8 billion
* 2030 estimate: $23.34 billion<ref>{{Cite web |title=Field Programmable Gate Array Market To Reach $23.34Bn By 2030 |url=https://www.grandviewresearch.com/press-release/global-fpga-market |access-date=2024-04-25 |website=www.grandviewresearch.com |language=en}}</ref>
===
A ''design start'' is a new custom design for implementation on an FPGA.
* 2005: 80,000<ref name="designstarts">Dylan McGrath, ''EE Times'', "[http://www.eetimes.com/conf/dac/showArticle.jhtml?articleID=164302400 Gartner Dataquest Analyst Gives ASIC, FPGA Markets Clean Bill of Health]". June 13, 2005. Retrieved February 5, 2009.</ref>
* 2008: 90,000<ref name="eweekly">
==
Contemporary FPGAs have ample [[logic gate]]s and RAM blocks to implement complex digital computations. FPGAs can be used to implement any logical function that an [[ASIC]] can perform. The ability to update the functionality after shipping, [[partial re-configuration]] of a portion of the design<ref>{{cite book| last1 = Wisniewski| first1 = Remigiusz| title = Synthesis of compositional microprogram control units for programmable devices| year = 2009| publisher = University of Zielona Góra| ___location = Zielona Góra| isbn = 978-83-7481-293-1| page = 153| url = http://zbc.uz.zgora.pl/Content/27955}}{{Dead link|date=February 2022 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.<ref name="FPGA">{{cite web|url=http://www.eecg.toronto.edu/~vaughn/challenge/fpga_arch.html|title=FPGA Architecture for the Challenge|work=toronto.edu|publisher=[[University of Toronto]]}}</ref>
As FPGA designs employ very fast I/O rates and bidirectional data [[Bus (computing)|buses]], it becomes a challenge to verify correct timing of valid data within setup time and hold time.<ref>{{cite book |last1=Oklobdzija |first1=Vojin G. |title=Digital Design and Fabrication |date=2017 |publisher=CRC Press |isbn=9780849386046 |url=https://books.google.com/books?id=VOnyWUUUj04C&dq=fpga+logic+gates+ram+blocks&pg=SA9-PA6}}</ref> [[Floorplan (microelectronics)|Floor planning]] helps resource allocation within FPGAs to meet these timing constraints.
Some FPGAs have analog features in addition to digital functions. The most common analog feature is a programmable [[slew rate]] on each output pin. This allows the user to set low rates on lightly loaded pins that would otherwise [[Electrical resonance|ring]] or [[Coupling (electronics)|couple]] unacceptably, and to set higher rates on heavily loaded high-speed channels that would otherwise run too slowly.<ref>{{cite web|url=http://wiki.altium.com/display/ADOH/FPGA+SI+Tutorial+-+Simulating+the+Reflection+Characteristics|title=FPGA Signal Integrity tutorial|work=altium.com|access-date=2010-06-15|archive-url=https://web.archive.org/web/20160307162907/http://wiki.altium.com/display/adoh/fpga+si+tutorial+-+simulating+the+reflection+characteristics|archive-date=2016-03-07|url-status=dead}}</ref><ref>[http://klabs.org/richcontent/fpga_content/DesignNotes/signal_quality/actel_drive_strength/index.htm NASA: FPGA drive strength] {{webarchive |url=https://web.archive.org/web/20101205230408/http://klabs.org/richcontent/fpga_content/DesignNotes/signal_quality/actel_drive_strength/index.htm |date=2010-12-05}}</ref> Also common are quartz-[[crystal oscillator]] driver circuitry, on-chip [[RC oscillator]]s, and [[phase-locked loop]]s with embedded [[voltage-controlled oscillator]]s used for clock generation and management as well as for high-speed serializer-deserializer (SERDES) transmit clocks and receiver clock recovery. Fairly common are differential [[comparator]]s on input pins designed to be connected to [[differential signaling]] channels. A few [[mixed signal]] FPGAs have integrated peripheral [[analog-to-digital converter]]s (ADCs) and [[digital-to-analog converter]]s (DACs) with analog signal conditioning blocks, allowing them to operate as a [[system on a chip]] (SoC).<ref>{{cite magazine |author=Mike Thompson |url=https://www.design-reuse.com/articles/16197/mixed-signal-fpgas-provide-green-power.html |title=Mixed-signal FPGAs provide GREEN POWER |magazine=Design & Reuse |date=2007-07-02}}</ref> Such devices blur the line between an FPGA, which carries digital ones and zeros on its internal programmable interconnect fabric, and [[field-programmable analog array]] (FPAA), which carries analog values on its internal programmable interconnect fabric.
=== Logic blocks ===
{{Main|Logic block}}
[[File:FPGA cell example.png|thumb|Simplified example illustration of a logic cell (LUT – [[lookup table]], FA – [[full adder]], DFF – [[D-type flip-flop]])]]
The most common FPGA architecture consists of an array of [[logic block]]s called configurable logic blocks (CLBs) or logic array blocks (LABs) (depending on vendor), [[I/O address|I/O pads]], and routing channels.<ref name="FPGA" /> Generally, all the routing channels have the same width (number of signals). Multiple I/O pads may fit into the height of one row or the width of one column in the array.
"An application circuit must be mapped into an FPGA with adequate resources. While the number of logic blocks and I/Os required is easily determined from the design, the number of routing channels needed may vary considerably even among designs with the same amount of logic. For example, a [[crossbar switch]] requires much more routing than a [[systolic array]] with the same gate count. Since unused routing channels increase the cost (and decrease the performance) of the FPGA without providing any benefit, FPGA manufacturers try to provide just enough channels so that most designs that will fit in terms of [[Lookup table#Hardware LUTs|lookup tables]] (LUTs) and I/Os can be [[Routing (electronic design automation)|routed]]. This is determined by estimates such as those derived from [[Rent's rule]] or by experiments with existing designs."<ref>{{Cite journal |last1=M.b |first1=Swami |last2=V.p |first2=Pawar |date=2014-07-31 |title=VLSI DESIGN: A NEW APPROACH |url=https://bioinfopublication.org/pages/article.php?id=BIA0002301 |journal=Journal of Intelligence Systems |language=En |volume=4 |issue=1 |pages=60–63 |issn=2229-7057}}</ref>
In general, a logic block consists of a few logical cells. A typical cell consists of a 4-input LUT, a [[Adder (electronics)|full adder]] (FA) and a [[D-type flip-flop]]. The LUT might be split into two 3-input LUTs. In ''normal mode'' those are combined into a 4-input LUT through the first [[multiplexer]] (mux). In ''arithmetic'' mode, their outputs are fed to the adder. The selection of mode is programmed into the second mux. The output can be either [[Synchronous circuit|synchronous]] or [[Asynchronous circuit|asynchronous]], depending on the programming of the third mux. In practice, the entire adder or parts of it are [[Shannon expansion|stored as functions]] into the LUTs in order to save [[Circuit utilization|space]].<ref>[http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf 2. CycloneII Architecture] {{Webarchive|url=https://web.archive.org/web/20101214055643/http://www.altera.com/literature/hb/cyc2/cyc2_cii51002.pdf |date=2010-12-14 }}. Altera. February 2007</ref><ref>{{cite web |url=http://www.altera.com/literature/hb/stratix-iv/stx4_5v1_01.pdf |title=Documentation: Stratix IV Devices |publisher=Altera.com |date=2008-06-11 |access-date=2013-05-01 |archive-url=https://web.archive.org/web/20110926214034/http://www.altera.com/literature/hb/stratix-iv/stx4_5v1_01.pdf |archive-date=2011-09-26 |url-status=dead}}</ref><ref>[http://www.xilinx.com/support/documentation/user_guides/ug070.pdf Virtex-4 FPGA User Guide] (December 1st, 2008). Xilinx, Inc.</ref>
=== Hard blocks ===
Modern FPGA families expand upon the above capabilities to include higher-level functionality fixed in silicon. Having these common functions embedded in the circuit reduces the area required and gives those functions increased performance compared to building them from logical primitives. Examples of these include [[Binary multiplier|multipliers]], generic [[Digital signal processor|DSP blocks]], [[Microprocessor|embedded processors]], high-speed I/O logic and embedded [[Computer memory|memories]].
Higher-end FPGAs can contain high-speed [[multi-gigabit transceiver]]s and ''hard IP cores'' such as [[processor core]]s, [[Ethernet]] [[Medium access control|medium access control units]], [[Conventional PCI|PCI]] or [[PCI Express]] controllers, and external [[memory controller]]s. These cores exist alongside the programmable fabric, but they are built out of [[transistor]]s instead of LUTs so they have ASIC-level performance and power consumption without consuming a significant amount of fabric resources, leaving more of the fabric free for the application-specific logic. The multi-gigabit transceivers also contain high-performance [[signal conditioning]] circuitry along with high-speed serializers and deserializers, components that cannot be built out of LUTs. Higher-level physical layer (PHY) functionality such as [[line coding]] may or may not be implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.
=== Soft core ===
[[File:Xilinx Zynq-7000 AP SoC.jpg|thumb|A [[Xilinx]] Zynq-7000 all-programmable system on a chip]]
An alternate approach to using hard macro processors is to make use of [[soft processor]] [[Semiconductor intellectual property core|IP cores]] that are implemented within the FPGA logic. [[Nios II]], [[MicroBlaze]] and [[Mico32]] are examples of popular softcore processors. Many modern FPGAs are programmed at ''run time'', which has led to the idea of [[reconfigurable computing]] or reconfigurable systems – [[CPU]]s that reconfigure themselves to suit the task at hand. Additionally, new non-FPGA architectures are beginning to emerge. Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.
===
In 2012 the coarse-grained architectural approach was taken a step further by combining the [[logic block]]s and interconnects of traditional FPGAs with embedded [[microprocessor]]s and related peripherals to form a complete [[System on a chip|system on a programmable chip]]. Examples of such hybrid technologies can be found in the [[Xilinx]] Zynq-7000 all [[programmable SoC]],<ref name="Xilinx-Inc-Oct-2011-8-K">{{cite web|url=http://edgar.secdatabase.com/520/95012311090713/filing-main.htm |title=Xilinx Inc, Form 8-K, Current Report, Filing Date Oct 19, 2011 |publisher=secdatabase.com |access-date =May 6, 2018}}</ref> which includes a 1.0 [[GHz]] dual-core [[ARM Cortex-A9]] MPCore processor [[Embedded system|embedded]] within the FPGA's logic fabric,<ref name="Xilinx-Inc-May-2011-10-K">{{cite web|url=http://edgar.secdatabase.com/1249/95012311055454/filing-main.htm |title=Xilinx Inc, Form 10-K, Annual Report, Filing Date May 31, 2011 |publisher=secdatabase.com |access-date =May 6, 2018}}</ref> or in the [[Altera]] Arria V FPGA, which includes an 800 MHz [[dual-core]] [[ARM Cortex-A9]] MPCore. The [[Atmel]] FPSLIC is another such device, which uses an [[Atmel AVR|AVR]] processor in combination with Atmel's programmable logic architecture. The [[Microsemi]] [[SmartFusion]] devices incorporate an ARM Cortex-M3 hard processor core (with up to 512 kB of [[Flash memory|flash]] and 64 kB of RAM) and analog [[peripheral]]s such as a multi-channel [[analog-to-digital converter]]s and [[digital-to-analog converter]]s in their [[flash memory]]-based FPGA fabric.{{cn|date=November 2022}}
=== Clocking ===
Most of the logic inside of an FPGA is [[synchronous circuit]]ry that requires a [[clock signal]]. FPGAs contain dedicated global and regional routing networks for clock and reset, typically implemented as an [[H tree]], so they can be delivered with minimal [[Clock skew|skew]]. FPGAs may contain analog [[phase-locked loop]] or [[delay-locked loop]] components to synthesize new [[clock frequencies]] and manage [[jitter]]. Complex designs can use multiple clocks with different frequency and phase relationships, each forming separate [[clock ___domain]]s. These clock signals can be generated locally by an oscillator or they can be recovered from a [[data stream]]. Care must be taken when building [[clock ___domain crossing]] circuitry to avoid [[Metastability (electronics)|metastability]]. Some FPGAs contain [[dual port RAM]] blocks that are capable of working with different clocks, aiding in the construction of building [[FIFO (computing and electronics)|FIFOs]] and dual port buffers that bridge clock domains.
=== 3D architectures ===
To shrink the size and power consumption of FPGAs, vendors such as [[Tabula (company)|Tabula]] and [[Xilinx]] have introduced [[three-dimensional integrated circuit|3D or stacked architectures]].<ref>Dean Takahashi, VentureBeat. "[https://venturebeat.com/2011/05/02/intel-connection-helped-chip-startup-tabula-raise-108m Intel connection helped chip startup Tabula raise $108M]." May 2, 2011. Retrieved May 13, 2011.</ref><ref name="lawrence">Lawrence Latif, The Inquirer. "[https://web.archive.org/web/20101029124903/http://www.theinquirer.net/inquirer/news/1811460/fpga-manufacturer-claims-beat-moores-law FPGA manufacturer claims to beat Moore's Law]." October 27, 2010. Retrieved May 12, 2011.</ref> Following the introduction of its [[28 nm|28 nm]] 7-series FPGAs, Xilinx said that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies<!--dice or dies is correct for integrated circuits — Wiktionary--> in one package, employing technology developed for 3D construction and stacked-die assemblies.
Xilinx's approach stacks several (three or four) active FPGA dies side by side on a silicon [[interposer]] – a single piece of silicon that carries passive interconnect.<ref name="lawrence" /><ref>EDN Europe. "[http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html Xilinx adopts stacked-die 3D packaging] {{Webarchive|url=https://web.archive.org/web/20110219182606/http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html |date=2011-02-19 }}." November 1, 2010. Retrieved May 12, 2011.</ref> The multi-die construction also allows different parts of the FPGA to be created with different process technologies, as the process requirements are different between the FPGA fabric itself and the very high speed 28 Gbit/s serial transceivers. An FPGA built in this way is called a ''[[Heterogeneous computing|heterogeneous]] FPGA''.<ref>{{Cite web|url=https://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf |archive-url=https://web.archive.org/web/20101105113516/http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf |archive-date=2010-11-05 |url-status=live|title=Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency|last=Saban|first=Kirk|date=December 11, 2012|website=xilinx.com|access-date=2018-11-30}}</ref>
Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting other dies and technologies to the FPGA using Intel's embedded multi_die interconnect bridge (EMIB) technology.<ref>{{cite web|url=http://www.intel.com/content/www/us/en/foundry/emib.html|title=Intel Custom Foundry EMIB|work=Intel|access-date=2015-07-13|archive-date=2015-07-13|archive-url=https://web.archive.org/web/20150713230215/http://www.intel.com/content/www/us/en/foundry/emib.html|url-status=dead}}</ref>
== Programming ==
{{See|Logic synthesis|Verification and validation|Place and route}}
To define the behavior of the FPGA, the user provides a design in a [[hardware description language]] (HDL) or as a [[schematic]] design. The HDL form is more suited to work with large structures because it's possible to specify high-level functional behavior rather than drawing every piece by hand. However, schematic entry can allow for easier visualization of a design and its [[Modular programming|component modules]].
Using an [[electronic design automation]] tool, a technology-mapped [[netlist]] is generated. The netlist can then be fit to the actual FPGA architecture using a process called ''[[place and route]]'', usually performed by the FPGA company's proprietary place-and-route software. The user will validate the results using [[Static timing analysis|timing analysis]], [[simulation]], and other [[verification and validation]] techniques. Once the design and validation process is complete, the binary file generated, typically using the FPGA vendor's proprietary software, is used to (re-)configure the FPGA. This file is transferred to the FPGA via a [[Serial communication|serial interface]] ([[JTAG]]) or to an external memory device such as an [[EEPROM]].
The most common HDLs are [[VHDL]] and [[Verilog]]. [[National Instruments]]' [[LabVIEW]] graphical programming language (sometimes referred to as ''G'') has an FPGA add-in module available to target and program FPGA hardware. Verilog was created to simplify the process making HDL more robust and flexible. Verilog has a C-like syntax, unlike VHDL.<ref>{{Cite web|title=Battle Over the FPGA: VHDL vs Verilog! Who is the True Champ?|url=https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/|access-date=2020-12-16|website=digilentinc.com|language=en-US|archive-date=2020-12-26|archive-url=https://web.archive.org/web/20201226074106/https://blog.digilentinc.com/battle-over-the-fpga-vhdl-vs-verilog-who-is-the-true-champ/|url-status=dead}}</ref>{{sps|{{subst|DATE}}|date=February 2024}}
To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called ''[[Semiconductor intellectual property core|intellectual property (IP) cores]]'', and are available from FPGA vendors and third-party IP suppliers. They are rarely free, and typically released under proprietary licenses. Other predefined circuits are available from developer communities such as [[OpenCores]] (typically released under [[free and open source]] licenses such as the [[GPL]], [[BSD license|BSD]] or similar license). Such designs are known as [[open-source hardware]].
In a typical [[design flow]], an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the [[Register-transfer level|RTL]] description in [[VHDL]] or [[Verilog]] is simulated by creating [[test bench]]es to simulate the system and observe results. Then, after the [[Logic synthesis|synthesis]] engine has mapped the design to a netlist, the netlist is translated to a [[Logic gate|gate-level]] description where simulation is repeated to confirm the synthesis proceeded without errors. Finally, the design is laid out in the FPGA at which point [[propagation delay]] values can be [[Back annotation|back-annotated]] onto the netlist, and the simulation can be run again with these values.
More recently, [[OpenCL]] (Open Computing Language) is being used by programmers to take advantage of the performance and power efficiencies that FPGAs provide. OpenCL allows programmers to develop code in the [[C programming language]].<ref>{{cite web|url=http://streamcomputing.eu/blog/2014-09-16/use-opencl-fpgas/|title=Why use OpenCL on FPGAs?|work=StreamComputing|date=2014-09-16|access-date=2015-07-17|archive-date=2017-01-01|archive-url=https://web.archive.org/web/20170101125857/https://streamcomputing.eu/blog/2014-09-16/use-opencl-fpgas/|url-status=dead}}</ref> For further information, see [[high-level synthesis]] and [[C to HDL]].
Most FPGAs rely on an [[static random-access memory|SRAM]]-based approach to be programmed. These FPGAs are in-system programmable and re-programmable, but require external boot devices. For example, [[flash memory]] or [[EEPROM]] devices may load contents into internal SRAM that controls routing and logic. The SRAM approach is based on [[CMOS]].
Rarer alternatives to the SRAM approach include:
* [[Fuse (electrical)|Fuse]]: one-time programmable. Bipolar. Obsolete.
* [[Antifuse]]: one-time programmable. CMOS. Examples: Actel SX and Axcelerator families; Quicklogic Eclipse II family.<ref name=EDN>{{cite web|url=https://www.edn.com/all-about-fpgas/|title=All about FPGAs|date=21 March 2006 }}</ref>
* [[Programmable read-only memory|PROM]]: programmable read-only memory technology. One-time programmable because of plastic packaging.{{clarify|reason=What's the issue with plastic packages?|date=July 2024}} Obsolete.
* [[EPROM]]: erasable programmable read-only memory technology. One-time programmable but with window, can be erased with ultraviolet (UV) light. CMOS. Obsolete.
* [[EEPROM]]: electrically erasable programmable read-only memory technology. Can be erased, even in plastic packages. Some but not all EEPROM devices can be in-system programmed. CMOS.
* [[Flash memory|Flash]]: flash-erase EPROM technology. Can be erased, even in plastic packages. Some but not all flash devices can be in-system programmed. Usually, a flash cell is smaller than an equivalent EEPROM cell and is, therefore, less expensive to manufacture. CMOS. Example: Actel ProASIC family.<ref name=EDN/>
In 2016, long-time industry rivals [[Xilinx]] (now part of [[AMD]]) and [[Altera]] (now part of [[Intel]]) were the FPGA market leaders.<ref>{{cite web |first=Paul |last=Dillien |work=EETimes | url=http://www.eetimes.com/author.asp?doc_id=1331443 | archive-url =https://web.archive.org/web/20190105015123/http://www.eetimes.com/author.asp?doc_id=1331443 |title=And the Winner of Best FPGA of 2016 is... |date=March 6, 2017 |access-date=September 7, 2017 |archive-date=January 5, 2019 }}</ref> At that time, they controlled nearly 90 percent of the market.
Both Xilinx and Altera provide [[proprietary software|proprietary]] [[electronic design automation]] software for [[Windows]] and [[Linux]] ([[Xilinx ISE|ISE]]/[[Vivado]] and [[Intel Quartus Prime|Quartus]]) which enables engineers to [[Hardware design|design]], analyze, [[simulate]], and [[Logic synthesis|synthesize]] ([[compile]]) their designs.<ref>{{Cite web|url=https://www.xilinx.com/products/design-tools/ise-design-suite.html|title=Xilinx ISE Design Suite|website=www.xilinx.com|access-date=2018-12-01}}</ref><ref>{{Cite web|url=https://www.altera.com/products/design-software/fpga-design/quartus-prime/overview.html|title=FPGA Design Software - Intel Quartus Prime|website=Intel|language=en|access-date=2018-12-01}}</ref>
In March 2010, [[Tabula (company)|Tabula]] announced their FPGA technology that uses [[Time-division multiplexing|time-multiplexed]] logic and interconnect that claims potential cost savings for high-density applications.<ref>{{cite web |title=Tabula's Time Machine — Micro Processor Report |url=http://www.tabula.com/news/M11_Tabula_Reprint.pdf |url-status=dead |archive-url=https://web.archive.org/web/20110410094902/http://www.tabula.com/news/M11_Tabula_Reprint.pdf |archive-date=2011-04-10}}</ref> On March 24, 2015, Tabula officially shut down.<ref>[http://www.bizjournals.com/sanjose/news/2015/02/11/tabula-to-shut-down-120-jobs-lost-at-fabless-chip.html Tabula to shut down; 120 jobs lost at fabless chip company] Silicon Valley Business Journal</ref>
On June 1, 2015, Intel announced it would acquire Altera for approximately [[US$]]16.7 billion and completed the acquisition on December 30, 2015.<ref>{{cite news|url=https://www.reuters.com/article/us-altera-m-a-intel-idUSKBN0OH2E020150601|title=Intel to buy Altera for $16.7 billion in its biggest deal ever|newspaper=Reuters|date=June 2015}}</ref>
On October 27, 2020, AMD announced it would acquire Xilinx<ref>{{cite news|url=https://www.amd.com/en/press-releases/2020-10-27-amd-to-acquire-xilinx-creating-the-industry-s-high-performance-computing|title=AMD to Acquire Xilinx, Creating the Industry's High Performance Computing Leader|date=October 2020}}</ref> and completed the acquisition valued at about US$50 billion in February 2022.<ref>{{cite news|url=https://www.reuters.com/technology/amd-closes-biggest-chip-acquisition-with-498-bln-purchase-xilinx-2022-02-14/|title=AMD closes record chip industry deal with estimated $50 billion purchase of Xilinx|newspaper=Reuters|date=February 2022}}</ref>
In February 2024 Altera became independent of Intel again.<ref name="Intel Launches Altera">{{Cite press release |title=Intel Launches Altera, Its New Standalone FPGA Company |url=https://www.intel.com/content/www/us/en/newsroom/news/intel-launches-altera-standalone-fpga-operation.html |access-date=2024-02-29 |website=Intel |language=en}}</ref>
Other manufacturers include:
* [[Achronix]], manufacturing SRAM based FPGAs with 1.5 GHz fabric speed<ref>{{Cite press release |url=http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing |title=Achronix to Use Intel's 22nm Manufacturing |date=2010-11-01 |work=Intel Newsroom |access-date=2018-12-01 |language=en-US |archive-date=2015-09-30 |archive-url=https://web.archive.org/web/20150930082224/http://newsroom.intel.com/community/intel_newsroom/blog/2010/11/01/chip-shot-achronix-to-use-intel-s-22nm-manufacturing |url-status=dead }}{{better source needed|date=September 2024}}</ref>
*[[Altium]], provides system-on-FPGA hardware-software design environment.<ref>{{cite book |last1=Maxfield |first1=Clive |title=The Design Warrior's Guide to FPGAs |date=16 June 2004 |publisher=Elsevier Science |isbn=9780080477138 |url=https://books.google.com/books?id=dnuwr2xOFpUC&dq=fpga+altium&pg=PA117}}</ref>
* Cologne Chip, German government-backed designer and producer of FPGAs<ref>{{Cite web |title=About the company – Cologne Chip |url=https://colognechip.com/about-the-company/ |access-date=2024-02-27 |language=en-US}}{{better source needed|date=September 2024}}</ref>
* [[Efinix]] offers small to medium-sized FPGAs. They combine logic and routing interconnects into a configurable XLR cell.{{cn|date=September 2024}}
* [[GOWIN Semiconductors]], manufacturing small and medium-sized SRAM and flash-based FPGAs. They also offer pin-compatible replacements for a few Xilinx, Altera and Lattice products.{{cn|date=September 2024}}
* [[Lattice Semiconductor]] manufactures [[Low-power electronics|low-power]] SRAM-based FPGAs featuring integrated configuration flash, [[instant-on]] and live [[Reconfigurable computing|reconfiguration]]
** [[SiliconBlue Technologies]] provides extremely low-power SRAM-based FPGAs with optional integrated [[Non-volatile memory|nonvolatile]] configuration memory; acquired by Lattice in 2011
* [[Microchip Technology|Microchip]]:
** [[Microsemi]] (previously [[Actel]]), producing [[antifuse]], flash-based, [[mixed-signal]] FPGAs; acquired by Microchip in 2018
** [[Atmel]], a second source of some Altera-compatible devices; also FPSLIC{{Clarify|reason=|date=December 2018}} mentioned above;<ref>{{Cite news|url=http://sourcetech411.com/2013/04/top-fpga-companies-for-2013/|title=Top FPGA Companies For 2013|date=2013-04-28|work=SourceTech411|access-date=2018-12-01|language=en-US|archive-date=2018-08-24|archive-url=https://web.archive.org/web/20180824135219/https://sourcetech411.com/2013/04/top-fpga-companies-for-2013/|url-status=dead}}</ref> acquired by Microchip in 2016
* QuickLogic manufactures ultra-low-power sensor hubs, extremely-low-powered, low-density SRAM-based FPGAs, with display bridges MIPI and RGB inputs; MIPI, RGB and LVDS outputs.<ref>{{Cite web|url=http://www.quicklogic.com/|title=QuickLogic — Customizable Semiconductor Solutions for Mobile Devices|website=www.quicklogic.com|publisher=QuickLogic Corporation|language=en|access-date=2018-10-07}}{{better source needed|date=September 2024}}</ref>
== Applications ==
{{See also|Hardware acceleration}}
An FPGA can be used to solve any problem which is [[computable]]. FPGAs can be used to implement a [[soft microprocessor]], such as the Xilinx [[MicroBlaze]] or Altera [[Nios II]]. But their advantage lies in that they are significantly faster for some applications because of their [[Parallel computing|parallel nature]] and [[Logic optimization|optimality]] in terms of the number of gates used for certain processes.<ref name="Xilinx-Inc-Apr-2006-8-K">{{cite web|url=http://edgar.secdatabase.com/657/110465906027899/filing-main.htm |title=Xilinx Inc, Form 8-K, Current Report, Filing Date Apr 26, 2006 |publisher=secdatabase.com |access-date =May 6, 2018}}</ref>
FPGAs were originally introduced as competitors to [[Complex programmable logic device|CPLDs]] to implement [[glue logic]] for [[printed circuit board]]s. As their size, capabilities, and speed increased, FPGAs took over additional functions to the point where some are now marketed as full [[systems on chip]]s (SoCs). Particularly with the introduction of dedicated [[Binary multiplier|multiplier]]s into FPGA architectures in the late 1990s, applications that had traditionally been the sole reserve of [[digital signal processor]]s (DSPs) began to use FPGAs instead.<ref>{{cite web|url=https://www.bdti.com/articles/info_eet0207fpga.htm|title=Publications and Presentations|work=bdti.com|access-date=2018-11-02|archive-url=https://web.archive.org/web/20100821182813/http://www.bdti.com/articles/info_eet0207fpga.htm|archive-date=2010-08-21|url-status=dead}}</ref><ref>{{cite web|url=https://www.eetimes.com/xilinx-aims-65-nm-fpgas-at-dsp-applications/#|title=Xilinx aims 65-nm FPGAs at DSP applications|work=EETimes|first=Mark|last=LaPedus|date=5 February 2007 }}</ref>
The evolution of FPGAs has motivated an increase in the use of these devices, whose architecture allows the development of hardware solutions optimized for complex tasks, such as 3D MRI image segmentation, 3D discrete wavelet transform, tomographic image reconstruction, or PET/MRI systems.<ref>{{Cite journal |last1=Alcaín |first1=Eduardo |last2=Fernández |first2=Pedro R. |last3=Nieto |first3=Rubén |last4=Montemayor |first4=Antonio S. |last5=Vilas |first5=Jaime |last6=Galiana-Bordera |first6=Adrian |last7=Martinez-Girones |first7=Pedro Miguel |last8=Prieto-de-la-Lastra |first8=Carmen |last9=Rodriguez-Vila |first9=Borja |last10=Bonet |first10=Marina |last11=Rodriguez-Sanchez |first11=Cristina |date=2021-12-15 |title=Hardware Architectures for Real-Time Medical Imaging |journal=Electronics |language=en |volume=10 |issue=24 |pages=3118 |doi=10.3390/electronics10243118 |issn=2079-9292|doi-access=free }}</ref><ref>{{Cite journal |last1=Nagornov |first1=Nikolay N. |last2=Lyakhov |first2=Pavel A. |last3=Valueva |first3=Maria V. |last4=Bergerman |first4=Maxim V. |date=2022 |title=RNS-Based FPGA Accelerators for High-Quality 3D Medical Image Wavelet Processing Using Scaled Filter Coefficients |journal=IEEE Access |volume=10 |pages=19215–19231 |doi=10.1109/ACCESS.2022.3151361 |s2cid=246895876 |issn=2169-3536|doi-access=free |bibcode=2022IEEEA..1019215N }}</ref> The developed solutions can perform intensive computation tasks with parallel processing, are dynamically reprogrammable, and have a low cost, all while meeting the hard real-time requirements associated with medical imaging.
Another trend in the use of FPGAs is [[hardware acceleration]], where one can use the FPGA to accelerate certain parts of an algorithm and share part of the computation between the FPGA and a general-purpose processor. The search engine [[Bing (search engine)|Bing]] is noted for adopting FPGA acceleration for its search algorithm in 2014.<ref name="BingFPGA">{{cite news |last1=Morgan |first1=Timothy Pricket |title=How Microsoft Is Using FPGAs To Speed Up Bing Search |url=https://www.enterprisetech.com/2014/09/03/microsoft-using-fpgas-speed-bing-search/ |access-date=2018-09-18 |publisher=Enterprise Tech |date=2014-09-03 }}{{Dead link|date=April 2025 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> {{as of|2018}}, FPGAs are seeing increased use as [[AI accelerator]]s including Microsoft's Project Catapult<ref name="ProjCatapult">{{cite web|url=https://www.microsoft.com/en-us/research/project/project-catapult/|title=Project Catapult|date=July 2018|website=Microsoft Research}}</ref> and for accelerating [[artificial neural network]]s for [[machine learning]] applications.
Originally,{{When|date=October 2018}} FPGAs were reserved for specific [[vertical application]]s where the volume of production is small. For these low-volume applications, the premium that companies pay in hardware cost per unit for a programmable chip is more affordable than the development resources spent on creating an ASIC. Often a custom-made chip would be cheaper if made in larger quantities, but FPGAs may be chosen to quickly bring a product to market. By 2017, new cost and performance dynamics broadened the range of viable applications.{{cn|date=December 2024}}
Other uses for FPGAs include:
* Space (with [[radiation hardening]]<ref>{{Cite web|url=https://www.militaryaerospace.com/articles/2016/06/radiation-hardened-space-fpga.html|title=FPGA development devices for radiation-hardened space applications introduced by Microsemi|website=www.militaryaerospace.com|access-date=2018-11-02|date=2016-06-03}}</ref>)
* [[Hardware security module]]s<ref name="auto">{{cite web|title=CrypTech: Building Transparency into Cryptography t |url=https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf |archive-url=https://web.archive.org/web/20160807180252/https://cryptech.is/wp-content/uploads/2016/02/CrypTech_Building_Transparency.pdf |archive-date=2016-08-07 |url-status=live}}</ref>
* High-speed financial transactions<ref>{{Cite web |last=Mann |first=Tobias |date=2023-03-08 |title=While Intel XPUs are delayed, here's some more FPGAs to tide you over |url=https://www.theregister.com/2023/03/08/intel_fpga_agilex/ |website=The Register}}</ref><ref>{{Cite conference |title=High Frequency Trading Acceleration Using FPGAs |last1=Leber |first1=Christian |last2=Geib |first2=Benjamin |last3=Litz |first3=Heiner |doi=10.1109/FPL.2011.64 |publisher=IEEE |date=September 2011 |conference=International Conference on Field Programmable Logic and Applications}}</ref>
* [[Retrocomputing]] (e.g. the MARS and [[MiSTer]] FPGA projects)<ref>{{cite web |url=https://www.retrorgb.com/the-diy-mister-handheld.html |title=The DIY MiSTer Handheld |date=16 December 2024 |access-date=}}</ref>
* Large scale integrated [[digital differential analyzer]]s, a form of an [[analog computer]] based on digital computing elements<ref>[https://people.ece.cornell.edu/land/courses/ece5760/DDA/index.htm DDA on FPGA - A modern Analog Computer]</ref>
=== Usage by United States military ===
FPGAs play a crucial role in modern military communications, especially in systems like the [[Joint Tactical Radio System]] (JTRS) and in devices from companies such as [[Thales Group|Thales]] and [[Harris Corporation]]. Their flexibility and programmability make them ideal for military communications, offering customizable and secure signal processing. In the JTRS, used by the US military, FPGAs provide adaptability and real-time processing, crucial for meeting various communication standards and encryption methods.<ref>{{Cite web |date=2004-12-01 |title=Software-defined radio and JTRS |url=https://www.militaryaerospace.com/computers/article/16710419/softwaredefined-radio-and-jtrs |access-date=2024-01-17 |website=Military Aerospace}}</ref>
== Security ==
Concerning [[hardware security]], FPGAs have both advantages and disadvantages as compared to ASICs or secure microprocessors. FPGAs' flexibility makes malicious modifications during [[Semiconductor device fabrication|fabrication]] a lower risk.<ref name="paper">{{Cite journal |doi=10.1109/MDT.2008.166 |title=Managing Security in FPGA-Based Embedded Systems |journal=IEEE Design & Test of Computers |volume=25 |issue=6 |pages=590–598 |year=2008 |last1=Huffmire |first1=Ted |last2=Brotherton |first2=Brett |last3=Sherwood |first3=Timothy |last4=Kastner |first4=Ryan |last5=Levin |first5=Timothy |last6=Nguyen |first6=Thuy D. |last7=Irvine |first7=Cynthia|bibcode=2008IDTC...25..590H |s2cid=115840 |hdl=10945/7159 |hdl-access=free }}</ref> Previously, for many FPGAs, the design [[bitstream]] was exposed while the FPGA loads it from external memory, typically during powerup. All major FPGA vendors now offer a spectrum of security solutions to designers such as bitstream [[encryption]] and [[authentication]]. For example, [[Altera]] and [[Xilinx]] offer [[Advanced Encryption Standard|AES]] encryption (up to 256-bit) for bitstreams stored in an external flash memory. [[Physical unclonable function]]s (PUFs) are integrated circuits that have their own unique signatures and can be used to secure FPGAs while taking up very little hardware space.<ref>{{Cite journal |last1=Babaei |first1=Armin |last2=Schiele |first2=Gregor |last3=Zohner |first3=Michael |date=2022-07-26 |title=Reconfigurable Security Architecture (RESA) Based on PUF for FPGA-Based IoT Devices |journal=Sensors |language=en |volume=22 |issue=15 |pages=5577 |doi=10.3390/s22155577 |issn=1424-8220 |pmc=9331300 |pmid=35898079 |bibcode=2022Senso..22.5577B |doi-access=free }}</ref>
FPGAs that store their configuration internally in nonvolatile flash memory, such as [[Microsemi]]'s ProAsic 3 or [[Lattice Semiconductor|Lattice]]'s XP2 programmable devices, do not expose the bitstream and do not need [[encryption]]. Customers wanting a higher guarantee of tamper resistance can use write-once, antifuse FPGAs from vendors such as [[Microsemi]].
With its Stratix 10 FPGAs and SoCs, [[Altera]] introduced a Secure Device Manager and [[physical unclonable function]]s to provide high levels of protection against physical attacks.<ref>{{cite web|url=https://www.intrinsic-id.com/eetimes-security-features-for-non-security-experts/|title=EETimes on PUF: Security features for non-security experts – Intrinsic ID|work=Intrinsic ID|date=2015-06-09|access-date=2015-07-12|archive-date=2015-07-13|archive-url=https://web.archive.org/web/20150713093531/https://www.intrinsic-id.com/eetimes-security-features-for-non-security-experts/|url-status=dead}}</ref>
In 2012 researchers Sergei Skorobogatov and Christopher Woods demonstrated that some FPGAs can be vulnerable to hostile intent. They discovered a critical [[Backdoor (computing)|backdoor vulnerability]] had been manufactured in silicon as part of the Actel/Microsemi ProAsic 3 making it vulnerable on many levels such as reprogramming crypto and [[access key]]s, accessing unencrypted bitstream, modifying [[low-level]] silicon features, and extracting [[Computer configuration|configuration]] data.<ref>{{cite book |volume=7428|pages=23–40|doi=10.1007/978-3-642-33027-8_2|series = Lecture Notes in Computer Science|year = 2012|last1 = Skorobogatov|first1 = Sergei|title=Cryptographic Hardware and Embedded Systems – CHES 2012|last2=Woods|first2=Christopher|isbn=978-3-642-33026-1|chapter=Breakthrough Silicon Scanning Discovers Backdoor in Military Chip}}</ref>
In 2020 a critical vulnerability (named Starbleed) was discovered in all Xilinx 7 series FPGAs that rendered bitstream encryption useless. There is no workaround. Xilinx did not produce a hardware revision. Ultrascale and later devices, already on the market at the time, were not affected.{{cn|date=July 2025}}
== Similar technologies ==
Historically, FPGAs have been slower, less energy efficient and generally achieved less functionality than their fixed ASIC counterparts. A study from 2006 showed that designs implemented on FPGAs need on average 40 times as much area, draw 12 times as much dynamic power, and run at one third the speed of corresponding ASIC implementations.<ref name="FPGA-ASIC-comparison">{{cite conference|doi=10.1145/1117201.1117205|chapter=Measuring the gap between FPGAs and ASICs|title=Proceedings of the international symposium on Field programmable gate arrays – FPGA'06|pages=21–30|year=2006|last1=Kuon|first1=Ian|last2=Rose|first2=Jonathan|isbn=1-59593-292-5|publisher=ACM|___location=New York, NY|chapter-url=http://ece.gmu.edu/coursewebpages/ECE/ECE448/S09/viewgraphs/Gap_between_FPGAs_and_ASICs.pdf|conference=|access-date=2017-10-25|archive-date=2010-06-22|archive-url=https://web.archive.org/web/20100622170541/http://ece.gmu.edu/coursewebpages/ECE/ECE448/S09/viewgraphs/Gap_between_FPGAs_and_ASICs.pdf|url-status=dead}}</ref>
Advantages of FPGAs include the ability to reprogram equipment in the field to fix [[Bug (computer programming)|bugs]] or make other improvements. Some FPGAs have the capability of [[partial re-configuration]] that lets one portion of the device be re-programmed while other portions continue running.<ref>{{Cite web|url=https://www.intel.com/content/www/us/en/programmable/documentation/ekx1496870149834.html|title=AN 818: Static Update Partial Reconfiguration Tutorial: for Intel Stratix 10 GX FPGA Development Board|website=www.intel.com|access-date=2018-12-01}}</ref><ref>{{Cite web|url=https://electronics.stackexchange.com/questions/45115/can-fpgas-dynamically-modify-their-logic|title=Can FPGAs dynamically modify their logic?|website=Electrical Engineering Stack Exchange|access-date=2018-12-01}}</ref> Other advantages may include shorter [[time to market]] and lower [[non-recurring engineering]] costs. Vendors can also take a middle road via [[FPGA prototyping]]: developing their prototype hardware on FPGAs, but manufacturing their final version as an ASIC after the design has been committed. This is often also the case with new processor designs.<ref>{{cite web|url=https://www.anandtech.com/show/14798/xilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells|archive-url=https://web.archive.org/web/20190827160514/https://www.anandtech.com/show/14798/xilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells|url-status=dead|archive-date=August 27, 2019|title=Xilinx Announces World Largest FPGA: Virtex Ultrascale+ VU19P with 9m Cells|first=Ian|last=Cutress|date=August 27, 2019|website=[[AnandTech]]}}</ref><!--[[User:Kvng/RTH]]-->
The primary differences between [[complex programmable logic device]]s (CPLDs) and FPGAs are [[Computer architecture|architectural]]. A CPLD has a comparatively restrictive structure consisting of one or more programmable [[Canonical normal form|sum-of-products]] logic arrays feeding a relatively small number of clocked [[Register (computing)|registers]]. As a result, CPLDs are less flexible but have the advantage of more predictable [[Latency (engineering)|timing delays]] and {{Citation needed span|text=a higher logic-to-interconnect ratio.|date=December 2018|reason=}} FPGA architectures, on the other hand, are dominated by [[Communications subsystem|interconnect]]. This makes them far more flexible (in terms of the range of designs that are practical for implementation on them) but also far more complex to design for, or at least requiring more complex [[electronic design automation]] (EDA) software. In practice, the distinction between FPGAs and CPLDs is often one of size as FPGAs are usually much larger in terms of resources than CPLDs. Typically only FPGAs contain more complex [[Functional unit|embedded functions]] such as [[Adder (electronics)|adders]], [[Binary multiplier|multipliers]], [[Computer memory|memory]], and [[SerDes|serializer/deserializers]]. Another common distinction is that CPLDs contain embedded [[flash memory]] to store their configuration while FPGAs usually require external [[non-volatile memory]] (but not always). When a design requires simple instant-on [[glue logic|(logic is already configured at power-up)]] CPLDs are generally preferred. For most other applications FPGAs are generally preferred. Sometimes both CPLDs and FPGAs are used in a single system design. In those designs, CPLDs generally perform glue logic functions and are responsible for "[[booting]]" the FPGA as well as controlling [[Reset (computing)|reset]] and boot sequence of the complete circuit board. Therefore, depending on the application it may be judicious to use both FPGAs and CPLDs in a single design.<ref>{{cite web|url=https://numato.com/kb/cpld-vs-fpga-differences-one-use/|title=CPLD vs FPGA: Differences between them and which one to use? – Numato Lab Help Center|website=numato.com|date=2017-11-29}}</ref>
== See also ==
{{Portal|Electronics}}
* [[FPGA Mezzanine Card]]
* [[CRUVI FPGA Card]] FPGA daughter card standard of Standardization Group for Embedded Technologies e.V. (SGET)
* [[List of HDL simulators]]
== References ==
{{
== Further reading ==
* {{cite book |first1=Hartmut F.-W. |last1=Sadrozinski |first2=Jinyuan |last2=Wu |title=Applications of Field-Programmable Gate Arrays in Scientific Research |year=2010 |publisher=Taylor & Francis |isbn=978-1-4398-4133-4
* {{cite book|title=Digital Circuit Design An Introduction Textbook |first=Niklaus |last=Wirth |publisher=Springer |year=1995 |isbn=978-3-540-58577-
* {{cite journal|title=An FPGA-Based Phase Measurement System |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=26 |pages=133–142 |first=Jubin |last=Mitra |publisher=IEEE |year=2018 |issue=1 |doi=10.1109/TVLSI.2017.2758807|bibcode=2018ITVL...26..133M |s2cid=4920719 |doi-access=free }}
* Mencer, Oskar et al. (2020). "The history, status, and future of FPGAs". Communications of the ACM. ACM. Vol. 63, No. 10. [[doi:10.1145/3410669]]
== External links ==
* {{YouTube|id=gUsHwi4M4xE|title=What is an FPGA?}}
* [https://www.ikalogic.com/2023/02/18/migrating-from-mcu-to-fpga.html Migrating from MCU to FPGA]
{{Electronic components}}
{{Semiconductor packages}}
{{Digital systems}}
{{Programmable Logic}}
{{Hardware acceleration}}
{{Authority control}}
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[[Category:Integrated circuits]]
[[Category:Semiconductor devices]]
[[Category:OpenCL compute devices| ]]
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[[Category:Hardware acceleration]]
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