Random test generator: Difference between revisions

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'''Random test generators''' (often abbreviated RTG or ISG<ref name=":0">{{Citation |title=Introduction to FORCE-RISCV |date=2023-02-21 |url=https://github.com/openhwgroup/force-riscv |publisher=OpenHW Group |access-date=2023-02-25}}</ref> for Instruction Stream Generator or Instruction Sequence Generator<ref name=":0" />) are a type of [[computer software]] that is used in [[functional verification]] of [[microprocessor]]s. Their primary use lies in providing input stimulus to a [[device under test]].

In a [[Logic simulation|simulation]]/[[Test bench|testbench]] verification environment, the simulator processes input created by the RTG and coverage monitors may be used to verify that the generator is properly testing the design.<ref>{{Cite web |title=Random Test Generator - Bridging the gap {{!}} BCS |url=https://www.bcs.org/membership-and-registrations/member-communities/software-testing-specialist-group/the-tester/newsletter-archive/random-test-generator-bridging-the-gap/ |access-date=2023-02-25 |website=www.bcs.org}}</ref>

Random test generators range in scope from simple [[Scripting language|scripts]] and parameterized [[Macro (computer science)|macro]]s that can be created in a matter of weeks to full featured systems requiring extensive software development. Random test generators are most often created by the designing organizations.

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==Dynamic Generators==

Dynamic generators incorporate significant knowledge about the architecture being tested. They enhance the ability of less-skilled users to generate complex tests that can hit hard-to-reach corner cases without stumbling on subtle programming pitfalls. This added knowledge, flexibility and ease-of-use is reflected in a more complex generator, and consequently the cost of creating and maintaining the generator are greater than for table-based or static generators.

==References==

{{Reflist}}

==External links==

* [http://www.haifa.ibm.com/dept/svt/papers/simulation/meth_date99.pdf IBM Genesys Pro] {{Webarchive|url=https://web.archive.org/web/20060316083416/http://www.haifa.ibm.com/dept/svt/papers/simulation/meth_date99.pdf |date=March 16, 2006 }}

* [http://www.obsidiansoft.com Obsidian Software RAVEN]

* [http://forge.ispras.ru/projects/microtesk MicroTESK], an [[open-source]] ISG developed by the [[Russian Academy of Sciences]]

* [httphttps://ieeexplore.ieee.org/Xploredocument/login.jsp?url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel5%2F9501%2F30140%2F01383278.pdf%3Farnumber%3D1383278&authDecision=-2031383278 IEEE article - A universal random test generator for functional verification of microprocessors and system-on-chip]

[[Category:Electronic circuit verification]]