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{{Short description|Association of electronic companies}}
{{redirect|ONFI|the medication under the brand name Onfi|clobazam}}
{{Infobox
|name = Open NAND Flash Interface Working Group
|image = Open NAND Flash Interface Working Group logo.gif
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}}
The '''Open NAND Flash Interface Working Group''' ('''ONFI''' or '''ONFi'''<ref>{{cite web |url=http://onfi.org/presentations/ |title=ONFI web site presentation page |publisher=[[ONFI]].org |
== History==
The group's goals did ''not'' include the development of a new consumer flash [[memory card]] format.<ref>{{cite web |url=http://www.onfi.org/about/faq/ |title=ONFI FAQ page |publisher=[[ONFI]].org |
{{cite web |url=http://onfi.org/wp-content/uploads/2009/02/onfi_whitepaper.pdf |
Thus, one of the main motivations for standardization of NAND flash was to make it easier to switch between NAND chips from different producers, thereby permitting faster development of NAND-based products and lower prices via increased [[competition (economics)|competition]] among manufacturers.
By 2006, NAND flash became increasingly a [[commodity]] product,<ref name="huffman-abraham">See this [http://www.onfi.org/presentations/IDF_S06_MEMS005_rev_H_USA.ppt presentation] {{Webarchive|url=https://web.archive.org/web/20070712092718/http://www.onfi.org/presentations/IDF_S06_MEMS005_rev_H_USA.ppt |date=2007-07-12 }} by Amber Huffman and Michael Abraham of [[Micron Technology|Micron]].</ref> like [[SDRAM]] or [[hard disk]] drives. It is incorporated into many [[personal computer]] and consumer electronics products such as [[USB flash drive]]s, [[MP3 player]]s, and [[solid-state drive]]s. Product designers wanted newer NAND flash chips, for example, to be as easily interchangeable as hard disks from different manufacturers.<ref name="huffman-abraham"/><ref>{{Cite news |title= Simplify Your Flash-Memory Interface |author= Jim Cooke |work= [[Dr. Dobb's Journal]] |date= September 25, 2006 |url= http://www.ddj.com/dept/embedded/193005155 |
=== Historical similarities ===
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=== Members ===
The ONFI consortium included manufacturers of NAND flash memory such as [[Hynix]], [[Intel]], [[Micron Technology]], [[Phison]], [[
Vendors of NAND flash-based consumer electronics and computing products are also members.
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Version 1.0 of this specification was released on December 28, 2006, and made available at no cost from the ONFI web site.
Samsung was still not a participant.<ref>{{Cite news |work= The Register |title= Vendors pledge to make Flash as easy to upgrade as RAM: Open Flash spec published |author= Tony Smith |date= January 22, 2007 |url= http://www.reghardware.co.uk/2006/05/11/intel_onfi_working_group_formed/ |
It specified:
* a standard physical interface ([[pinout]]) for NAND flash in [[Thin small-outline package|TSOP]]-48, WSOP-48, [[Land grid array|LGA]]-52, and [[Ball grid array|BGA]]-63 [[IC package|package]]s
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* improved data integrity by allowing optional [[Error detection and correction#Error-correcting memory|error-correcting code]] (ECC) features
A verification product was announced in June 2009.<ref>{{Cite news |title= Perfectus Announces
'''Version 2.3''' was published in August 2010. It included a protocol called EZ-NAND that hid ECC details.<ref>{{Cite news|url=http://www.eetimes.com/document.asp?doc_id=1257130|title=NAND specification adds error correction|author=Mark LaPedus|date=August 16, 2010|work=EE Times|
'''Version 3.0''' was published in March 2011. It required fewer chip-enable pins enabling more efficient [[printed circuit board]] routing.<ref>{{Cite web|url=http://www.onfi.org/~/media/ONFI/specs/ONFI_3_0_Gold.pdf|title=ONFI specification version 3.0|date=March 15, 2011|
A standard developed jointly with the [[JEDEC]] was published in October 2012.<ref>{{Cite news|url=http://www.jedec.org/news/pressreleases/jedec-and-open-nand-flash-interface-workgroup-publish-nand-flash-interface-intero|title=JEDEC and the Open NAND Flash Interface Workgroup Publish NAND Flash Interface Interoperability Standard|date=November 6, 2012|work=Press release|
'''Version 3.1''', published in october of 2012, includes errata to the original ONFI 3.0 specification, adds LUN SET/GET Features commands, and implements additional data setup and hold values for NV-DDR2 interface.
'''Version 3.2''', published on July 23, 2013, raised the data rate to 533 MB/s.<ref>{{Cite news|url=http://www.onfi.org/news-events/onfi-announces-publication-of-32-standard-pushes-data-transfer-speeds-to-533-mbsec|title=ONFI Announces Publication of 3.2 Standard, Pushes Data Transfer Speeds to 533 MB/sec|date=July 23, 2013|work=Press release|
'''Version 4.0''', published on April 17, 2014, introduced the NV-DDR3 interface increases the maximum switching speed from 533 MB/s to 800 MB/s, providing a performance boost of up to 50% for high performance applications enabled by solid-state NAND storage components.<ref>{{Cite news|url=http://www.businesswire.com/news/home/20140417005412/en/ONFI-Announces-Publication-4.0-Standard-Enabling-Generation#.U1fO6FdurA0|title=ONFI Announces Publication of 4.0 Standard, Enabling a New Generation I/O with Lower Power and Higher Bandwidth|date=April 17, 2014|work=Press release|publisher=ONFI}}</ref>
'''Version 4.1''', published on December 12, 2017, extends NV-DDR3 I/O speeds to 1066 MT/s and 1200MT/s.<ref>{{Cite web|url=http://www.onfi.org/specifications|title=Specifications - ONFi|website=www.onfi.org|access-date=2018-09-18}}</ref> For better signaling performance, ONFI 4.1 adds Duty Cycle Correction (DCC), Read and Write Training for speeds greater than 800MT/s, support for lower pin cap devices with 37.5 Ohms default output resistance, and devices which require data burst exit and restart for long data input and output pauses. For lower power, 2.5V Vcc support is added. ONFI 4.1 also includes errata to the ONFI 4.0 specification.
'''Version 4.2''', published on February 12, 2020, extends NV-DDR3 I/O speeds to 1333MT/s, 1466MT/s and 1600MT/s. The BGA-252b four channel package is introduced which has a smaller footprint than the existing BGA-272b four channel package. To enable higher IOPS multi-plane operations, addressing restrictions related to multi-plane operations are relaxed.<ref>{{Cite web|date=2020-02-12|title=Open NAND Flash Interface Specification Revision 4.2|url=https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_2-gold.pdf}}</ref>
'''Version 5.0''', Published in May 2021, ONFI5.0 extends NV-DDR3 I/O speeds up to 2400MT/s. A new NV-LPDDR4 lower power interface is introduced with speeds up to 2400MT/s. With the NV-LPDDR4 interface, an optional Data Bus Inversion (DBI) feature is defined. New smaller footprint BGA-178b, BGA-154b and BGA-146b packages are added. ONFI5.0 also includes other errata related to the ONFI4.2 specification.<ref>{{Cite web|last=|first=|date=25 May 2021|title=Open NAND Flash Interface Specification Revision 5.0|url=https://media-www.micron.com/-/media/client/onfi/specs/onfi_5_0_gold.pdf|website=}}</ref>
===Block Abstracted NAND===
ONFI created the Block Abstracted NAND addendum specification to simplify host controller design by relieving the host of the complexities of ECC, bad block management, and other low-level NAND management tasks. The ONFI Block Abstracted NAND revision 1.1 specification adds the high speed source synchronous interface, which provides up to a 5X improvement in bandwidth compared with the traditional asynchronous NAND interface.<ref>{{Cite web |title= Block Abstracted NAND specification version 1.1 |date= July 8, 2009 |url= http://www.onfi.org/~/media/ONFI/specs/BA_NAND_rev_1_1_Gold.pdf |
===NAND Connector===
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== External links ==
* {{official website|http://www.onfi.org/}}
{{authority control}}
[[Category:Computer memory]]
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