Multi-channel memory architecture: Difference between revisions

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{{Short description|Computer memory architecture}}

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{{confusing |date=October 2011}}

{{refimprove|date=January 2014}}

{{expand German|Dual Channel|date=March 2018}}

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In the fields of [[digital electronics]] and [[computer hardware]], '''multi-channel memory architecture''' is a technology that increases the data transfer rate between the [[DRAM]] memory and the [[memory controller]] by adding more channels of communication between them. Theoretically, this multiplies the data rate by exactly the number of channels present. Dual-channel memory employs two channels. The technique goes back as far as the 1960s having been used in [[IBM System/360 Model 91]] and in [[CDC 6600]].<ref name="JacobNg2007">{{cite book| first1=Bruce | last1 = Jacob | first2 = Spencer | last2 = Ng | first3=David | last3 = Wang|title= Memory systems: cache, DRAM, disk|year = 2007 | publisher = Morgan Kaufmann|isbn=978-0-12-379751-3|page= 318}}</ref>

Modern high-end desktop and workstation processors likesuch as the [[IntelAdvanced Micro Devices|AMD]] Core[[Ryzen i9Threadripper]] series and the [[AMDIntel]] Ryzen[[List Threadripperof Intel Core i9 processors|Core i9 Extreme Edition]] lineup support quad-channel memory. Server processors from the AMD [[Epyc]] series, alongand withthe variousIntel [[Xeon]]s platforms give support to memory bandwidth starting from quad-channel memorymodule layout to up to 12-channel layout.<ref>{{cite web |last1=Shilov |first1=Anton |title=AMD Confirms Twelve DDR5 Memory Channels For Zen 4 EPYC CPUs |url=https://www.tomshardware.com/news/amd-confirms-12-ddr5-memory-channels-on-genoa |website=Tom's Hardware |date=9 December 2021 |publisher=Future US Inc |access-date=22 April 2024}}</ref> In March 2010, AMD released [[Socket G34]] and Magny-Cours Opteron 6100 series<ref name = Opteron6100>{{cite web | publisher = AMD | title = Opteron 6000 Series Platform Quick Reference Guide | url = http://sites.amd.com/us/documents/48101a_opteron%20_6000_qrg_rd2.pdf | accessdateaccess-date = 2012-10-15 | archive-url = https://web.archive.org/web/20120512170219/http://sites.amd.com/us/Documents/48101A_Opteron%20_6000_QRG_RD2.pdf | archive-date = 2012-05-12 | url-status = dead }}</ref> processors with support for quad-channel memory. In 2006, Intel released chipsets that support quad-channel memory for its [[LGA771]] platform<ref>{{Citation | url = http://ark.intel.com/products/27746/Intel-5000P-Memory-Controller | publisher = Intel | title = 5000P memory controller}}.</ref> and later in 2011 for its [[LGA2011]] platform.<ref>{{Citation | url = http://www.techpowerup.com/138087/Intel-LGA2011-Socket-X68-Express-Chipset-Pictured.html | title = Intel LGA2011 socket x68 express chipset pictured | date = 10 January 2011 | publisher = Tech power up}}.</ref> Microcomputer chipsets with even more channels were designed; for example, the chipset in the [[AlphaStation]] 600 (1995) supports eight-channel memory, but the [[backplane]] of the machine limited operation to four channels.<ref>{{Citation | journal = HP | url = http://www.hpl.hp.com/hpjournal/dtj/vol7num1/vol7num1art7.txt | title = The Design and Verification of the AlphaStation 600 5-series Workstation | volume = 7 | number = 1 | author1 = John H. Zurawski | author2 = John E. Murray | author3 = Paul J. Lemmon | access-date = 2011-10-19 | archive-date = 2021-02-25 | archive-url = https://web.archive.org/web/20210225050210/https://www.hpl.hp.com/hpjournal/dtj/vol7num1/vol7num1art7.txt | url-status = dead }}.</ref> <!-- TODOTO-DO: Cite a machine where they actually used 8 channels. -->

== Dual-channel architecture ==

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=== Operation ===

Dual-channel architecture requires a dual-channel-capable motherboard and two or more [[DDR SDRAM|DDR]], [[DDR2 SDRAM|DDR2]], [[DDR3 SDRAM|DDR3]], [[DDR4 SDRAM|DDR4]], or [[DDR5 SDRAM|DDR5]] memory modules. The memory modules are installed into matching banks, each of which belongs to a different channel. The motherboard's manual will provide an explanation of how to install memory for that particular unit. A matched pair of memory modules may usually be placed in the first bank of each channel, and a different-capacity pair of modules in the second bank.<ref name= "Kingston520DDR">{{cite web | publisher = Infineon Technologies North America and Kingston Technology |date=September 2003 | url = http://www.kingston.com/newtech/MKF_520DDRwhitepaper.pdf | archiveurlarchive-url = https://web.archive.org/web/20110929024052/http://www.kingston.com/newtech/MKF_520DDRwhitepaper.pdf | title = Intel Dual-Channel DDR Memory Architecture White Paper | edition = Rev. 1.0 | format = PDF, 1021&nbsp;[[kilobyte|KB]] | accessdateaccess-date = 2007-09-06 | archivedatearchive-date = 2011-09-29}}</ref>

Modules rated at different speeds can be run in dual-channel mode, although the motherboard will then run all memory modules at the speed of the slowest module. Some motherboards, however, have compatibility issues with certain brands or models of memory when attempting to use them in dual-channel mode. For this reason, it is generally advised to use identical pairs of memory modules, which is why most memory manufacturers now sell "kits" of matched-pair DIMMs. Several motherboard manufacturers only support configurations where a "matched pair" of modules are used. A matching pair needs to match in:

* Capacity (e.g. 1024&nbsp;MB).

* Capacity (e.g. 1024&nbsp;MB). Certain Intel chipsets support different capacity chips in what they call Flex Mode: the capacity that can be matched is run in dual-channel, while the remainder runs in single-channel.

* Speed (e.g. PC5300).

* Speed (e.g. PC5300). If speed is not the same, the lower speed of the two modules will be used. Likewise, the higher latency of the two modules will be used.

* Memory timing, including (Column Address Strobe) latency or CL and other parameters.

* Same CAS Latency (CL) or Column Address Strobe.

* Number of chips and sides (e.g. two sides with four chips on each side).

* Matching sizeSize of rows and columns.

Of these requirements, only the clock and timing are absolutely required to match as the channels work in lockstep by definition. (If speed is not the same, the lower speed of the two modules will be used. Likewise, the higher latency of the two modules will be used.) The other requirements have loosened over time, starting with Intel's introduction of Flex Memory in 2004, which allows two modules of different size to work in a combination of dual and single channel, and AMD's introduction of an equivalent feature some time before 2015.

Dual-channel architecture is a technology implemented on motherboards by the motherboard manufacturer and does not apply to memory modules. Theoretically any matched pair of memory modules may be used in either single- or dual-channel operation, provided the motherboard supports this architecture.

Dual-channel architecture is a technology implemented on motherboards by the motherboard manufacturer and does not apply to memory modules. Theoretically any matched pair of memory modules may be used in either single- or dual-channel operation, provided the motherboard supports this architecture.

With the introduction of [[DDR5]], each DDR5 DIMM has two independent sub-channels 32 bits wide, compared to DDR4’s single 64-bit channel per DIMM.

=== Performance ===

Theoretically, dual-channel configurations double the memory bandwidth when compared to single-channel configurations. This should not be confused with [[double data rate]] (DDR) memory, which doubles the usage of DRAM bus by transferring data both on the rising and falling edges of the memory bus clock signals.

A benchmark performed by [[TweakTown]], using [[SiSoftware]] Sandra, measured around 70% increase in performance of a quadruple-channel configuration, when compared to a dual-channel configuration.<ref name="tweaktown-banchmark">{{cite web

| url = http://www.tweaktown.com/articles/4416/intel_x79_quad_channel_and_z68_dual_channel_memory_performance_analysis/index.html

| title = Intel X79 Quad Channel and Z68 Dual Channel Memory Performance Analysis

| date = 2011-11-16 | accessdate = 2013-11-30

| author = Shawn Baker | publisher = [[TweakTown]]

}}</ref>{{rp|p. 5}} Other tests performed by TweakTown on the same subject showed no significant differences in performance, leading to a conclusion that not all benchmark software is up to the task of exploiting increased parallelism offered by the multi-channel memory configurations.<ref name="tweaktown-banchmark" />{{rp|p. 6}}

=== {{Anchor|GANGED}}Ganged versus unganged ===

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| url = http://ixbtlabs.com/articles3/cpu/amd-phenom-x4-9850-ganged-unganged-p1.html

| title = AMD Phenom X4 Memory Controller in the Ganged/ Unganged Mode

| date = 2008-08-16 | accessdateaccess-date = 2014-01-09

| website = ixbtlabs.com

}}</ref> more modern implementations of dual-channel use the "unganged" mode by default, which maintains two 64-bit memory buses but allows independent access to each channel, in support of [[Multithreading (computer architecture)|multithreading]] with [[multi-core processor]]s.<ref name="ilsistemista-phenom">{{Cite web

| url = http://www.ilsistemista.net/index.php/hardware-analysis/3-the-phenom-phenomii-memory-controller-and-the-ganged-vs-unganged-question.html?start=1

| title = The Phenom / PhenomII memory controller: ganged vs unganged mode benchmarked

| date = 2010-06-17 | accessdateaccess-date = 2014-01-09

| author = Gionatan Danti | website = ilsistemista.net

}}</ref><ref name="amd-bkdg-10h">{{Cite web

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| title = BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors

| pages = 107–108

| date = 2013-01-11 | accessdateaccess-date = 2014-01-09

| website = amd.com

| quote = When the DCTs are in ganged mode, as specified by [The DRAM Controller Select Low Register] F2x110 [DctGangEn], then each logical DIMM is two channels wide. Each physical DIMM of a 2-channel logical DIMM is required to be the same size and use the same timing parameters. Both DCTs must be programmed with the same information (see 2.8.1 [DCT Configuration Registers]). When the DCTs are in unganged mode, a logical DIMM is equivalent to a 64-bit physical DIMM and each channel is controlled by a different DCT. Typical systems are recommended to run in unganged mode to benefit from the additional parallelism generated by using the DCTs independently. See 2.12.2 [DRAM Considerations for ECC] for DRAM ECC implications of ganged and unganged mode. Ganged mode is not supported for S1g3, S1g4, ASB2, and G34 processors.}}</ref>

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| title = JBOD (just a bunch of disks or just a bunch of drives)

| url = http://searchstorage.techtarget.com/definition/JBOD

| date = September 2005 | accessdateaccess-date = 2014-01-09

| first = Margaret | last = Rouse

| website = SearchStorage.TechTarget.com

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=== Operation ===

[[DDR3]] triple-channel architecture is used in the [[Intel]] [[Core i7]]-900 series (the Intel Core i7-800 series only support up to dual-channel). The LGA 1366 platform (e.g. Intel X58) supports DDR3 triple-channel, normally 1333 and 1600Mhz, but can run at higher clock speeds on certain motherboards. AMD Socket AM3 processors do not use the DDR3 triple-channel architecture but instead use dual-channel DDR3 memory. The same applies to the Intel Core i3, [[Core i5]] and Core i7-800 series, which are used on the [[LGA 1156]] platforms (e.g., [[Intel P55]]). According to Intel, a Core i7 with DDR3 operating at 1066&nbsp;MHz will offer peak data transfer rates of 25.6&nbsp;GB/s when operating in triple-channel [[interleaved memory|interleaved]] mode. This, Intel claims, leads to faster system performance as well as higher [[performance per watt]].<ref>{{Citation | publisher = Intel | title = X58 Product Brief |url= http://www.intel.com/Assets/PDF/prodbrief/x58-product-brief.pdf }}</ref>

When operating in triple-channel mode, [[memory latency]] is reduced due to interleaving, meaning that each module is accessed sequentially for smaller bits of data rather than completely filling up one module before accessing the next one. Data is spread amongst the modules in an alternating pattern, potentially tripling available memory bandwidth for the same amount of data, as opposed to storing it all on one module.

The architecture can only be used when all three, or a multiple of three, memory modules are identical in capacity and speed, and are placed in three-channel slots. When two memory modules are installed, the architecture will operate in dual-channel architecture mode.<ref name="support.intel.com">{{Citation | title = Desktop Boards – Triple Memory Modules | url=http://support.intel.com/support/motherboards/desktop/sb/CS-011965.htm#triple|publisher = Intel | access-date=2011-10-01|archive-date=2009-03-08|archive-url= https://web.archive.org/web/20090308093852/http://support.intel.com/support/motherboards/desktop/sb/CS-011965.htm#triple|url-status=dead}}, [https://www.intel.com/content/www/us/en/support/articles/000005657/boards-and-kits.html Single- and Multichannel Memory Modes]</ref>

=== Supporting processors ===

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=== Operation ===

Quad-channel memory debuted on Intel's Nehalem-EX [[DDR4LGA 1567]] hasplatform of Xeon CPUs, aka Beckton in 2010, and was introduced to the high end product line on the [[Intel X79]] [[LGA 2011]] platform with Sandy Bridge-E in late 2011. [[DDR4]] replaced [[DDR3]] on the [[Intel X99]] [[LGA 2011]] platform, aka Haswell-E, and is also used in AMD's [[Threadripper]] platform.<ref>[https://hothardware.com/news/amd-ryzen-threadripper-prey-4k-radeon-rx-vega-hits-in-july AMD Ryzen Threadripper And Vega Attack Prey At 4K, Quad GPUs Shred Blender, Radeon RX Vega Hits In July], "....with 16 cores and 32 threads with support for quad-channel DDR4 memory......"</ref> [[DDR3]] quad-channel architecture is used in the [[AMD]] [[Socket G34|G34]] platform and in the [[aforementioned Intel X79]]CPUs [[LGAprior 2011]]to platformHaswell. AMD processors for the [[Socket C32|C32]] platform and Intel processors for the [[LGA 1155]] platform (e.g., [[Intel Z68]]) use dual-channel DDR3 memory instead.

The architecture can be used only when all four memory modules (or a multiple of four) are identical in capacity and speed, and are placed in quad-channel slots. When two memory modules are installed, the architecture will operate in a dual-channel mode; whenWhen three memory modules are installed, the architecture will operate in a triple-channel mode.<ref name="support.intel.com" />

=== Performance ===

A benchmark performed by [[TweakTown]], using [[SiSoftware]] Sandra, measured around 70% increase in performance of a quadruple-channel configuration, when compared to a dual-channel configuration.<ref name="tweaktown-banchmark">{{cite web

| url = http://www.tweaktown.com/articles/4416/intel_x79_quad_channel_and_z68_dual_channel_memory_performance_analysis/index.html

| title = Intel X79 Quad Channel and Z68 Dual Channel Memory Performance Analysis

| date = 2011-11-16 | accessdateaccess-date = 2013-11-30

| author = Shawn Baker | publisher = [[TweakTown]]

}}</ref>{{rp|p. 5}} Other tests performed by TweakTown on the same subject showed no significant differences in performance, leading to a conclusion that not all benchmark software is up to the task of exploiting increased parallelism offered by the multi-channel memory configurations.<ref name="tweaktown-banchmark" />{{rp|p. 6}}

=== Supporting processors ===

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{{Col-break}}

'''AMD Threadripper:'''

* AMD Ryzen Threadripper 2nd gen 2990WX

* AMD Ryzen Threadripper 3rd gen 3960X

* AMD Ryzen Threadripper 3rd gen 3970X

* AMD Ryzen Threadripper 3rd gen 3990X

* AMD Ryzen Threadripper 3rd gen 3970X

* AMD Ryzen Threadripper 3rd gen 3960X

* AMD Ryzen Threadripper 2nd gen 2990WX

* AMD Ryzen Threadripper 2nd gen 2970WX

* AMD Ryzen Threadripper 2nd gen 2950X

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* AMD Ryzen Threadripper 1920X

* AMD Ryzen Threadripper 1900X

'''AMD Epyc:'''

* Epyc 7003 series processors

* Epyc 7002 series processors

* Epyc 7001 series processors

'''AMD Opteron:'''

* Opteron 6300-series "Abu Dhabi" (32&nbsp;nm)<ref name=Opteron6300>{{cite web | title = AMD Opteron 6300 Series processor Quick Reference Guide | url = https://www.amd.com/us/Documents/Opteron_6300_QRG.pdf | accessdateaccess-date = 2013-12-11 }}</ref>

* Opteron 6200-series "Interlagos" (32&nbsp;nm)<ref name=Opteron6200>{{cite web | title = AMD Opteron 6200 Series Processor Quick Reference Guide | url = https://www.amd.com/us/Documents/Opteron_6000_QRG.pdf | accessdateaccess-date = 2012-10-15 }}</ref>

* Opteron 6100-series "Magny-Cours" (45&nbsp;nm)<ref name="Opteron6100"/>

* Opteron 6200-series "Interlagos" (32&nbsp;nm)<ref name=Opteron6200>{{cite web | title = AMD Opteron 6200 Series Processor Quick Reference Guide | url = https://www.amd.com/us/Documents/Opteron_6000_QRG.pdf | accessdate = 2012-10-15 }}</ref>

* Opteron 6300-series "Abu Dhabi" (32&nbsp;nm)<ref name=Opteron6300>{{cite web | title = AMD Opteron 6300 Series processor Quick Reference Guide | url = https://www.amd.com/us/Documents/Opteron_6300_QRG.pdf | accessdate = 2013-12-11 }}</ref>

{{Col-break}}

'''Intel Core:'''

* Intel Core i9-10900X

* Intel Core i7-9800X

* Intel Core i9-7980XE

* Intel Core i9-7940X

* Intel Core i9-7900X

* Intel Core i7-7820X

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{{col-end}}

== SixHexa-channel architecture ==

Supported by [[Qualcomm Centriq]] server processors,<ref>{{cite news|last1=Kennedy|first1=Patrick|title=Qualcomm Centriq 2400 ARM CPU from Hot Chips 29|url=https://www.servethehome.com/qualcomm-centriq-2400-arm-cpu-hot-chips-29/|accessdateaccess-date=14 November 2017|publisher=Serve The Home|date=23 August 2017}}</ref>, and processors from the Intel Xeon Scalable processorsplatform.<ref>{{cite web |url=https://www.intel.in/content/www/in/en/products/processors/xeon/scalable/bronze-processors/bronze-3106.html |title=Intel® Xeon® Bronze 3106 Processor (11M Cache, 1.70 GHz) |date= |website=www.intel.in}}</ref>

== EightOcta-channel architecture ==

[[File:HP Z6 (极客湾Geekerwan) 029.png|thumb|alt=The image shows 4 RAM slots on the left and 4 on the right. The image center shows the socket and the AMD Ryzen Threadripper Pro 7995WX|Octa-channel setup with an AMD Ryzen Threadripper Pro 7995WX]]

Supported by [[Cavium#ThunderX2_SoCs|Cavium ThunderX2]] server processors, AMD's server processors from their [[Epyc]] platform, and the [[Threadripper|Threadripper PRO]] lineup of professional-class workstation processors.<ref>{{cite news|last1=Cutress|first1=Ian|title=AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2|url=http://www.anandtech.com/show/11183/amd-prepares-32-core-naples-cpus-for-1p-and-2p-servers-coming-in-q2|archive-url=https://web.archive.org/web/20170307171613/http://www.anandtech.com/show/11183/amd-prepares-32-core-naples-cpus-for-1p-and-2p-servers-coming-in-q2|url-status=dead|archive-date=March 7, 2017|access-date=7 March 2017|publisher=Anandtech|date=7 March 2017}}</ref><ref>{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 and OCP Platform Details|url=https://www.servethehome.com/cavium-thunderx2-ocp-platform-details/|access-date=14 November 2017|publisher=Serve the Home|date=9 November 2017}}</ref><ref>{{Cite web|last=Cutress|first=Ian|date=July 14, 2021|title=AMD Threadripper Pro Review: An Upgrade Over Regular Threadripper?|url=https://www.anandtech.com/show/16805/amd-threadripper-pro-review-an-upgrade-over-regular-threadripper|archive-url=https://web.archive.org/web/20210714131815/https://www.anandtech.com/show/16805/amd-threadripper-pro-review-an-upgrade-over-regular-threadripper|url-status=dead|archive-date=July 14, 2021|access-date=August 18, 2021|website=[[AnandTech]]}}</ref>

== Dodeca-channel architecture ==

Supported by [[AMD Epyc]] and [[Cavium#ThunderX2_SoCs|Cavium ThunderX2]] server processors.<ref>{{cite news|last1=Cutress|first1=Ian|title=AMD Prepares 32-Core Naples CPUs for 1P and 2P Servers: Coming in Q2|url=http://www.anandtech.com/show/11183/amd-prepares-32-core-naples-cpus-for-1p-and-2p-servers-coming-in-q2|accessdate=7 March 2017|publisher=Anandtech|date=7 March 2017}}</ref><ref>{{cite news|last1=Kennedy|first1=Patrick|title=Cavium ThunderX2 and OCP Platform Details|url=https://www.servethehome.com/cavium-thunderx2-ocp-platform-details/|accessdate=14 November 2017|publisher=Serve the Home|date=9 November 2017}}</ref>

[[File:AMD Epyc 9754 in Dual-CPU-Socket-Serversystem (极客湾Geekerwan) 07.png|thumb|Server system containing two AMD Epyc CPUs with one dodeca-channel per CPU (768 GiB RAM in total)]]

Dodeca-channel or 12-channel memory architecture is introduced with AMD's server processors from their [[Epyc#Fourth generation Epyc (Genoa, Bergamo and Siena)|Epyc 9004]] platform released in 2022, using [[DDR5]] memory.<ref>{{Cite web |last=Goetting |first=Chris |date=2022-11-10 |title=AMD 4th Gen EPYC 9004 Series Launched: Genoa Tested In A Data Center Benchmark Gauntlet |url=https://hothardware.com/reviews/amd-genoa-data-center-cpu-launch |access-date=2023-12-07 |website=HotHardware |language=en-us}}</ref>

== See also ==

* [[List of deviceinterface bandwidthsbit rates]]

* [[Lockstep (computing)]]

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[[de:Dual Channel]]

[[de:Triple Channel]]

[[es:Arquitectura de memoria multicanal]]

[[es:Doble canal]]

[[it:Dual channel]]

[[ja:デュアルチャネル]]