Address decoder: Difference between revisions

Revision as of 19:30, 13 January 2007

Revision as of 19:34, 13 January 2007

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Address decoders are fundamental building blocks for systems that use buses. They are represented in all integrated circuit families and processes and in all standard [[FPGA]] and [[ASIC]] libraries. They are discussed in introductory textbooks in digital logic design.

[[Category:Digital electronics| ]]